Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2001-07-13
2004-11-30
Phung, Anh (Department: 2824)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S069000
Reexamination Certificate
active
06826075
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to memory matrices, in particular memory matrices for MRAMs (Magnetoresistive Random Access Memory), i.e. nonvolatile magnetic memory elements including magnetic tunneling elements.
Random access semiconductor memories usually have a cell array including a matrix of column and row lines. Memory cells are provided at points where the column lines and the row lines intersect one another. In an MRAM, magnetic tunneling elements are typically used as memory elements.
Such a TMR element (TMR: tunneling magnetoresistance) includes, in principle, two magnetic layers, a hard-magnetic and a soft-magnetic layer. These layers are separated from one another by an insulating intermediate layer having a thickness of only a few atomic layers. The magnetizations in the two layers may be either in the same direction or oppositely directed. The insulating barrier between the magnetic layers is so thin that after a voltage has been applied, some electrons can pass through it. A so-called tunneling current flows. In this case, the intensity of the tunneling current depends on the orientation of the magnetization directions with respect to one another.
Data can be read from such a TMR element without altering the memory state thereof. Such a memory is written to by applying electric current to define the magnetization direction of the so-called “soft” magnetic layer. The content of the memory element is determined by the direction of the current. The currents required are relatively high (approximately 2.5 mA) particularly in the case of writing since the magnetization has to be effected by the magnetic field of a conductor through which current flows.
When writing to a TMR memory element, electric currents flow through the corresponding column and row lines, in which case only the column and row currents together can change the magnetization of the soft magnetic layer. In order to read the content of a memory cell, a voltage is passed onto the word line and the voltage drop across the tunneling resistance is measured, which represents the content of the memory cell.
In semiconductor memories, decoding the addresses is less complex in terms of circuitry if the respectively selected column lines lie directly next to one another. In the event of an access, however, it is then the case that the lines are also addressed simultaneously and have a corresponding signal applied to them. The problem then arises that, in the event of a current change, e.g. switching-on of the current flow, on one line, a corresponding interference current pulse is induced by inductive coupling on the neighboring line. This is particularly detrimental if opposite currents flow on the adjacent lines, because the induced interference currents then exactly counteract the actual write current. The degree of interference of the adjacent lines is particularly high if the logic levels “zero” and “one” alternate with one another on the adjacent lines, i.e. the current direction reverses.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory matrix which overcomes the above-mentioned disadvantages of the heretofore-known memory matrices of this general type and which reduces the negative effect of overcoupling from one line onto an adjacent line.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory matrix, including:
at least one cell array including lines, the lines including column lines and row lines;
the column lines and the row lines crossing one another at respective intersection points;
memory elements provided at the intersection points;
at least two of the lines having a relative position with respect to one another, the relative position with respect to one another changing along the at least two of the lines; and
the at least two of the lines are at least two of the column lines or at least two of the row lines.
In other words, the object of the invention is achieved by a memory matrix having at least one cell array including column lines and row lines at each of whose points of intersection memory elements are situated, the row lines and/or the column lines of a cell array in each case being disposed next to one another, wherein at least two column or row lines change their spatial configuration or position with respect to one another.
By virtue of the fact that, according to the invention, the respectively adjacent lines change their configurations in the direction in which they run, the effect achieved is that, with respect to a line, at least one of the adjacent lines changes. As a result of this, one line does not have the same neighboring lines across the entire cell array. This is advantageous in the event of simultaneous addressing of adjacent lines, as usually occurs during address decoding, because undesirable overcoupling or crosstalk effects between two lines can thus be reduced.
This change in the spatial configuration or relative positioning of adjacent lines advantageously is achieved by two lines in each case being crossed, since crossing two adjacent lines is the simplest realization in technological terms.
According to one embodiment of the invention, the memory matrix has a first and a second cell array, which are stacked in layers one above the other, in each case the column and/or the row lines of different layers essentially being opposite one another. Such stacking has the advantage that the storage density per chip area can be increased.
Preferably, a line is multiply crossed with an arbitrary and not always the same one of the column and/or row lines that are respectively provided alongside, i.e. the lines interchange their respective positions with one another by crossing one another. This makes it possible to achieve a further reduction of the coupling values between the lines originally disposed next to one another.
Besides changing the configuration of lines within a memory layer, in the case of a multilayer embodiment, such a change of the configuration can also be effected with regard to lines of another memory layer. This reduces the negative effect of overcoupling between adjacent lines of memory layers that are opposite one another.
In a further embodiment, the changing of the spatial to configuration of respectively different, adjacent column and/or row lines is only effected among the lines in a partial region of the column and row lines which is activated in the event of a memory access. This is advantageous because this allows a maximum decoupling between the lines of the partial region to be achieved with a small number of changes in the configuration, i.e. changes in the positioning of the lines. It suffices to reduce only the overcoupling within these segments, i.e. a plurality of lines that are adjacent or logically assigned to one another, because the segments are addressed only in succession. Lines that are addressed only simultaneously can influence one another. Unswitched or deenergized lines have no significant influence on the switching properties of the active lines. The active lines also do not influence the contents of the memory elements on the adjacent inactive lines. Nevertheless, relatively good decoupling is achieved for a multiplicity of possible bit patterns.
Preferably, it may be provided that the memory matrix is constructed, with regard to the changes of the spatial configuration of its lines, such that the order of the column and/or row lines is the same at opposite edges of the memory matrix. This makes it possible to avoid an additional circuit outlay in the realization of address decoders. Such an additional circuit outlay arises if the address lines are unordered or have an order which deviates from the original order. This is important in particular because, in the case of MRAM memories, circuitry of the column and row lines at both edges of the cell array is expedient. Furthermore, it may preferably be provided that the cell arrays or their column and/or row lines are mirror-symmetrical with res
Gogl Dietmar
Hönigschmid Heinz
Röhr Thomas
Greenberg Laurence A.
Hur J. H.
Infineon - Technologies AG
Locher Ralph E.
Phung Anh
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