Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-08
2004-08-24
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000
Reexamination Certificate
active
06781199
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device comprising a bipolar transistor having an insulating gate and a method of manufacturing the semiconductor device.
2. Description of the Background Art
In power electronics for driving a motor or the like, an IGBT (Insulated Gate Bipolar Transistor) has mainly been used as a switching element based on a characteristic in a region in which a rated voltage is 300 V or more.
FIG. 27
is a sectional view showing a structure of a conventional trench gate type IGBT (TIGBT). As shown in
FIG. 27
, an N
+
buffer layer
32
is formed on a P
+
substrate
31
and an N
−
layer
33
is formed on the N
+
buffer layer
32
.
A P base region
35
is selectively formed on the N
−
buffer layer
33
, and furthermore, an N
+
emitter region
36
is selectively formed in a surface of the P base region
35
. The P base region
35
can be formed by diffusing a P-type impurity and the N
+
emitter region
36
can be formed by diffusing an N-type impurity having a high concentration.
A trench
37
is formed to reach the upper layer portion of the N
−
layer
33
adjacently to the N
+
emitter region
36
through the P base region
35
, and a gate electrode
39
is buried in the trench
37
through a gate insulating film
38
formed on an internal wall of the trench
37
. The gate electrode
39
is formed of polysilicon.
A region of the P base region
35
opposed to the gate electrode
39
through the gate insulating film
38
is defined as a channel region. An interlayer insulating film
40
is formed over a large part of a surface of the N
+
emitter region
36
and the gate insulating film
38
, an emitter electrode
42
is formed over a part of the surface of the N
+
emitter region
36
(a portion excluding the large part) and a surface of the P base region
35
, and a collector electrode
43
is formed on a back face of the P
+
substrate
31
.
FIG. 28
is a sectional view showing a structure of a carrier stored TIGBT (CSTBT; Carrier Stored Trench-gate Bipolar Transistor devised by the inventors. As shown in
FIG. 28
, the TIGBT is different from the TIGBT shown in
FIG. 27
in that an N layer
34
is formed between the N
−
layer
33
and the P base region
35
. The N layer
34
is provided for storing a carrier in a region which is shallower than a bottom portion of the trench
37
.
Next, the operation of the IGBTs (TIGBT and CSTBT) shown in
FIGS. 27 and 28
will be described.
In the structures shown in
FIGS. 27 and 28
, when a predetermined collector voltage VCE is set between the emitter electrode
42
and the collector electrode
43
and a predetermined gate voltage VGE to bring an ON state is applied between the emitter electrode
42
and the gate electrode
39
, a channel region in the P base region
35
is inverted to have an N type so that a channel is formed.
An electron is injected from the emitter electrode
42
into the N
−
layer
33
(N layer
34
) through the channel. By the electron thus injected, a forward bias is applied between the P
+
substrate
31
and the N
−
layer
33
(N
+
buffer layer
32
), a hole is injected from the P
+
substrate
31
, a resistance value of the N
−
layer
33
is considerably reduced and a current capacity of the IGBT is enhanced. Thus, the IGBT can reduce the resistance value of the N
−
layer
33
by the injection of the hole from the P
+
substrate
31
.
Next, an operation of the IGBT from an ON state to an OFF state will be described. In the structures shown in
FIGS. 27 and 28
, the gate voltage VGE applied in the ON state between the emitter electrode
42
and the gate electrode
39
is changed into an OFF state such that “0” or a backward bias is applied.
Consequently, the channel region inverted to the N type is returned to the P type so that the injection of the electron from the emitter region
42
is also stopped. By the stop of the injection of the electron, the injection of the hole from the P
+
substrate
31
is also stopped. Then, the electron and the hole which are stored in the N
−
layer
33
(N
+
buffer layer
32
) go through the collector electrode
43
and the emitter electrode
42
respectively or are recombined with each other and are annihilated.
In the case of the TIGBT shown in
FIG. 27
, a MOS structure of the surface is reduced to approximately {fraction (1/10)} as compared with a plane gate type IGBT. Therefore, a characteristic can be enhanced. Moreover, a current flows to an N region interposed between the P base regions of the adjacent cells over the surface in the plane gate type IGBT. In this region, a voltage drop is great.
However, the gate electrode
39
is formed in a direction of a depth through the P base region
35
in the TIGBT. Consequently, the N
−
layer
33
interposed between the P base regions
35
is not present in a current path. Therefore, an operation characteristic can be enhanced.
In the CSTBT shown in
FIG. 28
, the N layer
34
is formed under the P base region
35
. Therefore, the hole sent from the P
+
substrate
31
can be prevented from reaching the emitter electrode
42
. Consequently, the hole is stored under the P base region
35
and an ON-state voltage can be more reduced than that in the TIGBT.
An IGBT having a trench gate structure shrinks to {fraction (1/10)} or more as compared with the plane gate type so that the number of gates is increased. Therefore, there is a problem in that a gate capacity is increased. In order to solve the problem, there has been a method of increasing a cell size to reduce the number of gates. If this method is employed, however, the ON-state voltage is raised in the TIGBT and the ON-state voltage is less raised and a breakdown voltage is dropped in the CSTBT. Therefore, the problem cannot be solved practically.
FIG. 29
is a graph showing a relationship between a trench space between the adjacent trenches (a distance between the trenches and a distance between opposed trench ends) and an ON-state voltage in each of the TIGBT and CSTBT.
FIG. 30
is a graph showing a relationship between the trench space and a breakdown voltage in each of the TIGBT and the CSTBT. In
FIGS. 29 and 30
, a curve LT indicates the characteristic of the TIGBT and a curve LC indicates the characteristic of the CSTBT.
Conventionally, the trench space in each of the TIGBT and the CSTBT has been designed to 3 &mgr;m. In
FIGS. 29 and 30
, the trench space is equal to or less than approximately 11 &mgr;m. If the trench space is 11 &mgr;m, a cell size is increased to three times as large as that in the conventional art and a gate capacity is reduced to ⅓.
In
FIG. 29
, the ON-state voltage is not greatly changed even if the trench space is increased in the CSTBT as shown in the curve LC, while the ON-state voltage is raised to such a level as not to be negligible with an increase in the trench space in the TIGBT as shown in the curve LT.
In
FIG. 30
, the breakdown voltage of the TIGBT is less dropped even if the trench space is increased as shown in the curve LT, while the breakdown voltage is rapidly dropped with an increase in the trench space in the CSTBT as shown in the curve LC, and particularly, approximates to 0 V if the trench space exceeds 5 &mgr;m.
In the conventional TIGBT and CSTBT, thus, the ON-state voltage is raised or the breakdown voltage is dropped. Therefore, there is a problem in that the trench space to reduce the gate capacity cannot be increased.
In common to the IGBTs (TIGBT and CSTBT), moreover, there is a problem in that a parasitic bipolar transistor (BIP-Tr) formed by the N
−
layer
33
(the N layer
34
in the CSTBT shown in FIG.
28
), the P base region
35
and the N
+
emitter region
36
is present.
When the parasitic BIP-Tr is operated, the IGBT cannot be controlled and is broken down. Since the CSTBT forms the N layer
34
, a
Lewis Monica
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Wilczewski Mary
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