Low power buffer implementation

Details Low power buffer implementation Low power buffer implementation

2002-06-21

2004-11-09

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06816994

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to buffers which are used to detect transitions in the power-consumption mode of an electronic device.
BACKGROUND OF THE INVENTION
Some electronic memory and processor devices have a low-power consumption or “sleep” mode in which a circuit within an electronic device temporarily shuts down during relatively long periods of unuse. Buffers are used to detect when it is necessary to “wake up” and restore power to the device. These buffers tend to be fast buffers with a symmetrical response because such buffers are advantageously used in other parts of a memory and/or processor device where high speed symmetrical switching is required. However, such symmetry is not always necessary during the condition when power is restored to a circuit, because a restore-power event is relatively rare and is not timing-critical. Additionally, fast buffers with symmetrical response tend to be complex and consume large amounts of power. Accordingly, use of such a buffer to detect a “wake up” condition tends to consume a large amount of power when the device is in the sleep mode.
BRIEF SUMMARY OF THE INVENTION
In one aspect, the invention provides a less complex and lower power buffer for detecting a “wake up” condition and which enables a plurality of high current buffers which are respectively connected to a plurality of signal lines. The high current buffers are disabled when in a sleep mode and are enabled by the low power buffer detecting the “wake up” condition.
In another aspect, the invention provides a method of determining when an electronic device should be enabled in a “wake-up” condition, including the steps of monitoring a line which indicates a wake-up condition with a low-power buffer; and enabling a plurality of high-current buffers when a wake-up condition is detected.
In yet another aspect, the invention provides a structure and method which uses a combination of a higher power high current buffer for detecting when a sleep mode is entered, and a lower power buffer for detecting a wake-up condition. The buffer combination is used to disable and enable a plurality of high current buffers.


REFERENCES:
patent: 5392221 (1995-02-01), Donath et al.
patent: 5526318 (1996-06-01), Slemmer et al.
patent: 5896338 (1999-04-01), Landgraf et al.
patent: 6256252 (2001-07-01), Arimoto
patent: 6281723 (2001-08-01), Tailliet
patent: 2003/0117875 (2003-06-01), Lee et al.
Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers, Mel Bazes, IEEE Journal of Solid-State Circuits, vol. 26, No. 2, Feb. 1991, pp. 165-168.

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