Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-12-31
2004-08-24
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S708000, C438S725000, C438S745000, C438S748000, C438S753000
Reexamination Certificate
active
06780780
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method for removing Si-needles of a wafer, and especially to one method for removing Si-needles formed during the manufacturing processes of deep trenches on the wafer.
BACKGROUND OF THE INVENTION
During the manufacturing processes of semiconductors, the main application of manufacturing deep trenches is to use wide surface areas to form the capacitors of dynamic random access memories (DRAMs). However, when deep trenches are formed on a wafer, the edges of the wafer do not be washed during the photolithography in order to improve the unity of the edges of the wafer etched by the dry etching and the chemical mechanical polishing. Because the edges of the wafer do not be washed, the yellow light will defocus on the edges of the wafer, and after the manufacturing processes of a reactive ion etching, the Si-needles will be produced. The Si-needles are silicon needle substances and kinds of ancillary products from ill-manufacturing processes of the deep trenches. If the Si-needles are not removed, they will become particle sources and reduce the yields at a level of 15%.
Please refer to FIG.
1
(
a
). FIG.
1
(
a
) is a flow chart of removing the deep trench Si-needles according to the prior art. At first, a photoresist layer on the frontsideside surface of the wafer is formed for protecting the patterns and the edges of the wafer are washed at a distance about 2 mm. Then, the Si-needles are removed by a chemical dry etching. Finally, the photoresist layer is removed.
Please refer to FIG.
1
(
b
). FIG.
1
(
b
) is a schematic diagram of the area washed during the process of washing edge in FIG.
1
(
a
). In which, the reference number
11
denotes the pattern unit, the reference number
12
denotes the area covered by the photoresist, the number
13
denotes the area uncovered by the phototresist, the reference number
14
denotes the edge of the wafer, and the reference number
15
denotes the boundary of the area washed during the process of washing edge. If the shapes of the deep trenches uncovered by the photoresist layer in the area
13
are not removed completely by the chemical dry etching, what is called shell-model defect will be produced. Because the trenches of the wafer become deeper from generation to generation during the manufacturing processes and the Si-needles always deposit after the manufacturing processes of the deep trenches, it is necessary to extend the etching time of the chemical dry etching for removing the Si-needles completely.
Besides, the disadvantages of the methods for removing the Si-needles according to the prior arts are time consumption and high cost. For example, when the deep trench Si-needles formed from the manufacturing processes of a 0.175 &mgr;m semiconductor are removed, the etching time of each wafer is 270 seconds (4.5 minutes), so that each lot of wafers will cost 6480 seconds (108 minutes)=1.8 hours. The total manufacturing time including etching, transfer, pumping down, and vent etc. steps of each lot of wafers is 4 hours. Thereto, it's necessary to rotate the quartz tube of the chemical dry etching tool once after the quartz tube thereof is used per 13 hours. Moreover, the quartz tube must be replaced and the Teflon transfer tube must be cleaned once after the quartz tube and the Teflon transfer tube are used per 52 hours. Therefore, the frequencies of the preventive maintenance of the chemical dry etching tool and the consumption of quartz tubes will increase rapidly when the manufacturing time of each lot of wafers extends.
Because of the technical disadvantage described above, the applicant keeps on carving unflaggingly to develop “method for removing the deep trench Si-needles of wafer” through wholehearted experience and
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for removing the Si-needles from the manufacturing processes of the deep trenches of a wafer.
It is another object of the present invention to provide a method for removing the deep trench Si-needles from the manufacturing processes of a wafer with less time and less cost.
The present invention provides a method for removing Si-needles formed during the processes of manufacturing deep trenches on a wafer. The method includes steps of forming a photoresist layer, removing a specific area of the photoresist layer, proceeding a first etching and a second etching and finally removing the photoresist layer on the frontside surface of the wafer. Forming a photoresist layer means to form a photoresist layer on a frontside surface of the wafer. Removing a specific area of the photoresist layer is used for exposing the Si-needles. The first etching is used for removing the SI-needles by an etching solution etching from a backside surface of the wafer back to the frontside surface of the wafer, and the second etching is used for removing the residual slices.
Preferably, the Si-needles are disposed around periphery of the wafer.
Preferably, the Si-needles are produced during a manufacturing process of the wafer.
Preferably, the step of removing a specific area of the photoresist layer is by means of washing away photoresist on the edge of a wafer.
Preferably, the first etching is a wet etching used to remove the Si-needles.
Preferably, the residual slices are silicon nitride (SiN) slices.
Preferably, the second etching is a dry etching used to remove the residual slices.
Preferably, the specific area is 1 mm to 2 mm away from the edge of the wafer.
Preferably, the photoresist layer covers and protects an area of dummy patterns from being etched by the etching solution.
Preferably, the step of the first etching further includes steps of turning the frontside surface of the wafer downward to be placed on a wafer chuck having pluralities of chuck pins in a wafer-backside etching machine, holding the wafer tightly with the chuck pins, protecting patterns of the wafer having the frontside surface downward by nitrogen gas (N
2
) and etching an upward backside surface of the wafer. Etching the upward backside surface of the wafer includes a step of removing the Si-needles by the etching solution via an action of etching from the backside surface of the wafer backside to the frontside surface of the wafer.
Preferably, the wafer-backside etching machine has a working surface raised by a packing.
Preferably, the working surface has a flange structure on an edge thereof.
Preferably, the flange structure and the chuck pins have a naked zone therebetween.
Preferably, the naked zone is etched during the etching back process of the etching solution.
Preferably, the first etching further includes a step of raising the chuck pins for holding the wafer after the working surface is raised.
Preferably, after the first etching the manufacturing process further includes a displacement process to readjust a position where the chuck pins hold the wafer for completely removing the Si-needles originally covered by the chuck pins.
Preferably, the displacement process includes steps of opening the chuck pins for releasing the wafer, accelerating the wafer chuck, decelerating the wafer chuck, closing the chuck pins for holding the wafer, and proceeding the first etching again for etching the Si-needles originally covered by the chuck pins.
Preferably, the positions of the wafer originally held by the chuck pins are exposed via the displacement process.
Preferably, the second etching is a reactive ion etching.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed descriptions and accompanying drawings, in which:
REFERENCES:
patent: 5874366 (1999-02-01), Sporer et al.
patent: 6162739 (2000-12-01), Sumnitsch et al.
patent: 6245678 (2001-06-01), Yamamoto et al.
patent: 6395646 (2002-05-01), Liu
patent: 6649077 (2003-11-01), Tsai et al.
Jan Jia-Shing
Liu Yueh-Liang
Ni Chih-Jung
Norton Nadine G.
Tran Binh X.
Winbond Electronics Corp.
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