Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-10-16
2004-08-24
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S081000, C326S083000, C326S063000, C327S333000
Reexamination Certificate
active
06781413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level conversion circuit for converting a signal on a lower power voltage side to a signal on a higher power voltage side, and relates in particular to a level conversion circuit for which an operation at the power voltage rise time is stabilized.
2. Related Background Arts
A semiconductor integrated circuit employs multiple power voltages to reduce the consumption of power by an internal circuit. For example, an internal power voltage used for an internal circuit is generated from an externally supplied a higher power voltage, and the internal power voltage is supplied to the internal circuit to reduce the consumption of power by the internal circuit. Since an output signal generated by the internal circuit is a lower voltage internal signal, at the front stage of an output circuit, a level conversion circuit converts the level of this signal into a signal for the higher external power source. As another example semiconductor integrated circuit which uses multiple power voltages, when a lower power voltage first circuit outputs a signal to a higher power voltage second circuit, at the output stage of the first circuit, the level conversion circuit converts a lower voltage signal into a higher voltage signal.
FIG. 13
is a circuit diagram showing a conventional level conversion circuit. VccL denotes a lower power voltage and VccH denotes a higher power voltage, while a P denotes a P channel transistor and an N denotes an N channel transistor. The lower power voltage VccL is 3 V, for example, and the higher power voltage VccH is 5 V, for example.
In a level converter
10
, the level conversion circuit converts a signal A on the lower power voltage side into a signal X on the higher power voltage side; the signal A and a signal /A (bar A; this same descriptive convention is employed hereinafter) for the inverted phase, which is generated by an inverter constituted by transistors P
1
and N
2
, are respectively transmitted to the gates of transistors N
6
and N
4
; the respective gates of transistors P
3
and P
5
are cross-connected to the drains of transistors P
5
and P
3
, while the sources of both transistors are connected to the higher power voltage VccH; and a node /B is connected to an output buffer circuit, constituted by transistors P
7
and N
8
, which is connected to the higher power voltage VccH.
During normal operation, when the signal A on the lower power voltage side is at level H (3 V), the inverted signal /A goes to level L (0 V), the transistor N
6
is rendered conductive and the transistor N
4
is rendered non-conductive, and the node /B is reduced to level L. As the level of the node /B is reduced, the transistor P
3
is rendered conductive, the level of the node B is raised to the level of the higher power voltage VccH, and the transistor P
5
is rendered non-conductive. As a result, the node /B is fully reduced to level 0 V, the transistor N
8
of the output buffer circuit is rendered non-conductive, and the transistor P
7
is rendered conductive, so that the output X goes to level H (5 V). That is, the signal A on the lower power voltage side (3 V) is converted into the signal B on the higher power voltage side (5 V). When the signal A is at level L, the transistor N
4
is rendered conductive and the transistor N
6
is rendered non-conductive, and since the inverted phase operation is performed, the output X goes to level L. Thus, since the node /B becomes the level of higher power voltage, the transistor P
7
of the output buffer circuit is rendered fully off.
As is described above, in the level conversion circuit of the level converter
10
, the node B of one of the transistors P
3
and P
5
, the respective gates and drains of which are cross-connected, is employed to render on or off the transistor P
5
, and an H level voltage is generated at the other node /B.
FIG. 14
is a diagram showing the power voltage relationships for a semiconductor integrated circuit. Normally, a lower power voltage generator
12
uses the higher power voltage VccH to generate the lower power voltage VccL. Therefore, when the power is on and the higher power voltage VccH rises, accordingly, the lower power voltage VccL also rises. On the higher power voltage side in
FIG. 13
, the signal X, obtained by level conversion, is transmitted to output circuits
14
and
16
, located between the circuit on the lower power voltage side and the circuit on the higher power voltage side, and outputs OUT
1
and OUT
2
are driven by the high driving capabilities of the output circuits
14
and
16
. Therefore, the power voltages of the output circuits
14
and
16
are the higher power voltage VccH.
FIG. 15
is a graph for explaining the problem presented by the level conversion circuit in FIG.
13
. When the externally applied higher power voltage VccH rises while the power is on, the nodes B and /B in the level conversion circuit may go to a level midway between the higher power voltage level and the ground level, and a penetration current may flow across the transistors P
7
and N
8
of the output buffer circuit. Accordingly, the signal X on the higher power voltage side becomes to a level midway between level H (VccH) and level L (0 V). At this level, the signal X generates a strong penetration current that passes through the output circuits
14
and
16
in FIG.
14
.
Specifically, the lower power voltage VccL rises as the higher power voltage VccH rises, but this rise in the lower power voltage VccL is unsatisfactory by the penetration current generated by the initial unstabilized operation of the level conversion circuit. In this initial state, one of the signals A and /A on the lower voltage side can not rise to the level H, and neither of the transistors N
4
and N
6
can be rendered conductive. If the higher power voltage VccH rises under these conditions, both of the nodes B and /B rise and stay at a level lower than the high power voltage VccH by the threshold voltage Vth of the transistors P
3
and P
5
(see FIG.
15
). Therefore, the nodes B and /B are maintained at the middle level, the penetration current flows across the transistors P
7
and N
8
, and the signal X on the higher voltage side also goes to the middle level, which causes a strong penetration current to the output circuits
14
and
15
to which the signal X is supplied. As a result, the lower power voltage generator
12
can not raise the lower power voltage VccL and this state is continued, unchanged. In the worst case, after the power-on a normal operation of the device is not possible.
SUMMARY OF THE INVENTION
It is, therefore, one objective of the present invention to provide a level conversion circuit for which the operation at the power voltage rise time is stabilized.
To achieve this objective, according to one aspect of the invention, a level conversion circuit for converting a first signal at a lower power source side into a second signal at a higher power source side, which is higher than the lower power source, comprises:
first and second transistors, provided at a ground side and controlled by the first signal and an inverted signal there of;
third and fourth transistors gates and drains of which are cross-connected, provided at the higher power source side and connected to the first and second transistors respectively; and
an initialization circuit for, at a higher power voltage rise time, reducing (or raising), along a current path, a level of either a first node located between the first and third transistors, or a second node located between the second and fourth transistors, to a ground voltage (or to a voltage of the higher power source).
According to a preferred embodiment of the invention, the initialization circuit includes an initialization transistor circuit which is located between one node of either the first or the second node and the ground, and which is rendered conductive during a period in which the voltage of the higher power source rises and the voltage of the lower power source does not ris
Kaneko Yuki
Kihara Fukuji
Arent Fox PLLC.
Fujitsu Limited
Tan Vibol
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