Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-02
2004-02-10
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06691290
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a new method and algorithm for routing second order of metal.
(2) Description of the Prior Art
The creation of Integrated Circuits (IC) comprises the creation of millions of transistors that form a semiconductor chip. The inherent complexity of the design and the layout of a semiconductor chip can only be addressed with automated software and hardware design tools whereby the emphasis is on automated software support without which the design of a semiconductor chip would be prohibitively complex and expensive.
The process of creating a semiconductor chip must, even with the help of complex hardware and mostly software support functions, be further approached in a relatively organized manner. This manner of organization is conventionally implemented by using either gate arrays or standard cells as the basic units for circuit integration within the scope of creating a semiconductor chip.
Gate arrays lend themselves to the objective of creating complex semiconductor devices because gate arrays have a fixed number of identical sites whereby each site comprises a number of basic and simple circuit elements. Functional characteristics of a complex chip can on a first level be implemented by interconnecting logic circuits that provide relatively basic logic functions such as inverters, and, or and nand gates, transfer gates and the like. A gate array can then further be used to interconnect the first level functions on a second level of interconnect by specifying the interconnections between the first level created circuit functions. A netlist is thereby used, which provides the interconnections between circuit elements of the gate array. It can readily be accepted that, in view of the complexity and the extent of the design of a semiconductor chip, a design aid such as a netlist must be maintained under control of a software support function.
The second basic approach that has been highlighted above, that is the use of standard cells for the creation of complex semiconductor chips, is based on the use of a number of standard circuit functions referred to as cells. While the gate array is of relatively limited design, the cells that are used as standard cells for the design of a semiconductor chip can be extended in functional capability leading from relative simple cell designs such as a simple logic gate to cells of a block-level component whereby each cell can contain a relatively complex semiconductor function such as a Random Access Memory (RAM) cell, a Read Only Memory (ROM) cell and the like. Again the standard cells that are used for the design of a semiconductor chip are maintained by software support functions whereby typically an inventory of cells is maintained on a data base referred to as a cell library. From the cell library standard cells can be retrieved for use in chip design whereby it is common practice to use numbers of standard cells for functional interconnection, thereby creating relatively complex circuit functions.
The above highlighted basic components that are used to create a complex semiconductor chip must be conductively interconnected, using a place and route tool, in order to create a functional chip design. For these conductive interconnections, design rules are used, which assure that the interconnections are provided in an optimum manner from the point of view of chip functionality and chip reliability. The place and route tool typically addresses first level of metal interconnects and accesses a standard library in which are stored data relating to the standard components (gate arrays or standard cells) that are used for the creation of the functional semiconductor chip. Layout of the higher levels of metal, such as second, third level of metal, etc., are typically addressed by separate software support packages. Since the first level metal (metal-1) place and route tool forms the first level of conductive interconnect, it is to be expected that this first level pick and route support optimally lends itself to assuring that higher levels of conductive interconnect are provided in am optimum manner. Stating this in another manner it can be said that the interaction between the standard library and the first level of metal interconnect place and route tool can be provided such that the standard library is not negatively affected by the first level of metal interconnect place and route tool. The invention addresses this aspect of chip layout and design in specifically assuring that the standard library can be applied for 0.13 &mgr;m conductive interconnect technology.
U.S. Pat. No. 6,308,309 B1 (Gan et al.) shows place holding library elements for defining routing paths.
U.S. Pat. No. 5,856,9274 (Greidinger et al.) is a method for automatically routing circuits involving a router tool.
U.S. Pat. No. 5,483,461 (Lee et al.) is a routing algorithm method involving router tool/program.
U.S. Pat. No. 6,298,469 B1 (Yin) reveals a circuit design method using a place and route process.
SUMMARY OF THE INVENTION
A principle objective of the invention is to create a new rule for routing a layer of interconnect metal whereby this new rule is applied to first level of metal (metal-1) routing.
In accordance with the objectives of the invention a new algorithm is provided for the routing of metal-1 layer of interconnect. The invention provides and algorithm that assures that a new (layout or design) rule, which is provided for metal interconnects for 0.13 &mgr;m or less technology, can be implemented.
This new layout rule requires that, at the metal-1 level of interconnect, for metal interconnect have a metal width that is larger than or equal to 0.3 &mgr;m and a parallel run length of the two adjacent lines that is larger or equal to 1 &mgr;m and the minimum space between two adjacent metal lines must be larger than 0.22 &mgr;m. The metal-1 layer is the only layer that uses both the standard library and the place-and-route tool, the implementation of the new layout rule assures that the standard library can continued to be used for technology of 0.13 &mgr;m or less.
The invention creates a grid of horizontal and vertical lines across a plane, the plane is the plane in which metal-1 is to be created. This plane overlies an (underlying) layer of metal, such as metal of a basic cell component, to which interconnects must be established by the metal-1 pattern. By using the coordinates of the intersects of the horizontal and the vertical lines, these intersects can be assigned attributes that indicate whether a particular intersect should or should not be connected to the underlying layer of metal. Using these attributes of the intersects of the imaginary metal grid, an intersect that can be interconnected with the underlying layer of metal can now be extended beyond that intersect, making a maximum pattern available for interconnect to a pin type in the underlying layer of metal. After the pattern of metal-1 has been created in this manner over the complete surface of the underlying layer of metal (of for instance a cell), the created metal-1 pattern can be analyzed for potential rule violations.
REFERENCES:
patent: 5483461 (1996-01-01), Lee et al.
patent: 5721959 (1998-02-01), Nakamura et al.
patent: 5831870 (1998-11-01), Folta et al.
patent: 5856927 (1999-01-01), Greidinger et al.
patent: 6075934 (2000-06-01), Chiluvuri et al.
patent: 6298469 (2001-10-01), Yin
patent: 6308309 (2001-10-01), Gan et al.
Ackerman Stephen B.
Garbowski Leigh M.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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