Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
2000-08-11
2004-06-29
Perveen, Rehana (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S043000, C710S100000, C711S145000, C439S101000
Reexamination Certificate
active
06757751
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Field of the Invention
A computer system needs memory to store instructions and data that are processed by the central processing unit (CPU). In a typical computer, the CPU communicates with the memory via a bus, that sets a limit on the amount of parallel information (width) that can move in a single time unit. Memory comes in special chips known as DRAM (dynamic random access memory), which are packaged together in industry-standard modules. The chips are arranged in a line on a printed circuit board (PCB), with the memory chips either on a single side (SIMM, or Single In-Line Memory Module) or on both sides (DIMM, or Dual In-Line Memory Module). There are industry-standard machines for connecting memory chips to a board and then soldering the connections between the chips' input/output (I/O) pins and the metal circuits printed on the board, because the cost and yield respectively increase and decrease when the same work is done by hand, even by skilled (yet thus more expensive) labor. The size of the memory chip on a SIMM or DIMM has become standardized to increase the manufacturability and lower the cost of the completed memory module. A memory module PCB, also known as a ‘memory bank’, will have a set of connectors between its on-board circuitry and the computer system bus additionally, it often has subordinate governing and special logic circuits to help manage the U/O flow between the memory module and the rest of the computer system.
There are two goals that designers, manufacturers, and users of memory modules strive for While the amount of memory that can be stored on a single memory chip has been increasing steadily the amount of memory necessary for smooth and fast operation of a computer system has also been increasing. Individual memory banks have gone through several generations in the past decade alone, moving from 8 megabytes to 16 megabytes to 32 megabytes to 64 megabytes per module, with 128 megabyte modules on the commercial horizon. Over roughly the same time, however, the minimum system RAM for a normal personal computer (PC) has shifted from 640K to 65MB. So one goal is to maximize, for the capacity of a given generation of memory chip, the total amount of memory that can be contained on a memory bank, when the memory bank is a SIMM (or DIMM) incorporating a number of such memory chips, within the same geometric limits for the memory banks.
At the same time that the amount of memory desired has increased, the price for memory has decreased (almost exponentially), just as the price paid for a given power computer has also decreased. This has created some unpleasant trade-offs for computer manufacturers, and for memory bank manufacturers. For the same amount of memory each year they will get less money, meaning that they constantly need ways to provide more memory for less cost. For this reason, anything that increases the manufacturing yield of a memory bank with a particular memory capacity, find anything that decreases the cost of manufacturing a memory bank, is a useful and valuable advance. Thus, decreasing the density of on-board circuitry for a memory bank necessary to provide memory capacity is a desirable result, since it decreases the cost and increases the yield of production of such. Two design elements that increase the cost, and decrease the yield, of producing a memory bank are, first, increasing the number of pin connectors needed to attain a given number of I/O connections between the memory bank and the bus; and second, requiring manual assembly and soldering of a given number of pin connections between the memory chips and the PCB the memory bank. The more pins that must be connected, the fewer banks can be manufactured in a given amount of time, and the lower the manufacturing yield will be (since there are that many more chances for a pin connection to be inaccurately made). If the number of connections required can be cut by a significant percentage, then the overall productivity for a given memory bank capacity will be increased.
Technological advances are costly to implement, and for certain implementations it is desirable to use less costly technology interchangeably with system configurations which can use higher technology. For example, sometimes it is desirable to use 16-meg chips with systems that support 64-meg technology. In such a configuration, a 64 or 72 bit wide data bus using 64-megabit (8M times 8) chips can be used. If the system is designed for 8M times 8 chips, the JEDEC standard is for a 12 times 11 address scheme (i.e., 12 row address bits and 11 column address bits). In such a scheme, only one bank is required to read all 64 or 72 bits, and thus only a single RAS signal is needed. However, 64 megabit chips all utilize 3.3 volt technology which for several reasons is quite expensive and thus, while fewer chips can be used to store the same information, these fewer chips in the aggregate are more expensive than using 16 megabit chips manufactured in 5-volt technology. For example. 8, 8 times 8 chips can be used to store the same amount of information as is stored in 32, 4 times 4 chips. However, the 32 4 times 4 chips are much cheaper in the aggregate than the 8.8 times 8 chips, and thus for many applications, even though more chips are involved, it is desirable to use the 5-volt technology and 32, 4 times 4 chips. As a result, computer designers have struggled to increase the amount of memory accessible within a given physical format or module even though there has been a more costly alternative of increasing the memory bank's capacity by buying higher-priced but higher-capacity individual memory chips for that bank.
Moreover, bus limitations are now one of the bottleneck points to computer designs. The more that off-bus smarts can be designed into the memory bank, the less the load on the system for overhead, in managing memory addressing, becomes. A number of methods have already been designed to deal with part of this problem.
For example, a computer's memory typically includes one or more memory banks (or memory components) connected in parallel such that each memory component stores one set of data, such as a word or double word, per memory address. The memory controller communicates with, and interprets commands from, the CPU to the memory modules. For example, the CPU issues a command and an address which are received and translated by the memory controller. The memory controller, in turn, applies appropriate command signals and row and column addresses to the memory modules. Examples of such commands include a row address strobe (RAS), column address strobe (CTS), write enable (WEE), and possibly a clock signal (CLK). (The line or bar over the acronym for a symbol generally indicates, that the active state for the particular signal is a logical low value.) In response to the commands and addresses, data is transferred between the CPU and the memory modules. Each time a memory changing update instruction must be issued, however, the computer's cycle overhead is increased. Techniques that do not require the CPU to manage all details of memory storage decrease this overhead and thus indirectly increase performance; therefore, design elements of a memory bank that decrease the demand on the CPU to issue memory change updates indirectly increase performance.
Secondly, because the majority of program execution through the CPU is sequential in nature (operation
1
, operation
2
, operation
3
. . . , operation
50
), program execution very often proceeds along a row of memory. When in page mode, the memory controller compares the row address of the memory location currently being accessed with the row address for the next memory access. If the row addresses are the same (known as a “page hit”), then the memory controller continues asserting the RAS control signal at the end of a current bus cycle. Because the memory already has t
Mai Rijue
Perveen Rehana
LandOfFree
High-speed, multiple-bank, stacked, and PCB-mounted memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-speed, multiple-bank, stacked, and PCB-mounted memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-speed, multiple-bank, stacked, and PCB-mounted memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3343959