Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-18
2004-02-03
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S310000, C257S311000
Reexamination Certificate
active
06686621
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which includes a capacitor having a damascene pillar-type cell.
2. Description of the Background Art
Conventionally, a damascene pillar-type cell structure has been used for capacitors in semiconductor devices. A damascene pillar-type cell is formed by applying a damascene pillar process and is a cell in a form where a capacitor lower electrode
112
, a capacitor dielectric film
113
and a capacitor upper electrode
114
are layered on each other so as to form a bell shape, as shown in FIG.
13
. As for the form, it is similar to a stack type capacitor and the characteristic thereof is that misalignment in a photomechanical process for a capacitor lower electrode can be overcome by means of the following process. In the following, a summary of a conventional process for a capacitor of a damascene pillar-type cell is given. Here, the structures of a semiconductor substrate
101
, source/drain regions
102
, a gate insulating film
103
, a gate electrode
104
, an interlayer insulating film
105
and a contact plug
106
are similar to those in a conventional art and, therefore, the description of the process is omitted.
A capacitor having a conventional damascene pillar-type cell is formed by a conventional process as shown in
FIG. 14
such that after forming contact plug (poly Si or metal such as TiN, W)
106
in interlayer insulating film
105
, the entirety of the upper surfaces of both interlayer insulating film
105
and contact plug
106
is covered with a silicon nitride film
107
. Here, the film thickness of a representative silicon nitride film
107
is several tens of nm.
Next, as shown in
FIG. 15
, the upper surface of silicon nitride film
107
is further covered with a silicon oxide film
108
. Here, the thickness of silicon oxide film
108
depends on height of the cell and is approximately several hundreds of nm. Next, as shown in
FIG. 16
, a contact hole
109
is created in silicon oxide film
108
so that the surface of silicon nitride film
107
is exposed. Next, as shown in
FIG. 17
, the bottom of contact hole
109
is further etched so as to penetrate silicon nitride film
107
and to extend contact hole
109
to the degree that contact plug
106
and interlayer insulating film
105
are slightly etched.
Here, as for the creation of contact hole
109
, an opening is created in silicon oxide film
108
by using a photomechanical process and etching wherein what is important is that there is an advantage in a capacitor having a damascene pillar-type cell that a positional shift between the opening and contact plug
106
can be overcome, unless contact hole
109
completely misses contact plug
106
unlike in a conventional stack-type cell. In
FIG. 17
the case is shown where a misalignment is purposefully formed in order to emphasize the above point. Here, in practice, framing, such as of TEOS, may be carried out in some cases after creating the opening for the purpose of making the diameter of the contact hole smaller.
In addition, silicon nitride film
107
is etched in a self-aligning manner and, in the case that contact hole
109
misses contact plug
106
at this point in time, a portion of interlayer insulating film
105
and a portion of contact plug
106
below silicon nitride film
107
are etched. Usually, the etching rate of contact plug
106
is faster than that of interlayer insulating film
105
and, therefore, a structure in a step form as shown in
FIG. 17
is formed.
Next, as shown in
FIG. 18
, the opening of contact hole
109
is filled in with, and the upper surface of silicon oxide film
108
is covered with, a metal
110
which will become capacitor lower electrode
112
. The filling in method is not particularly limited, however, a CVD (Chemical Vapor Deposition) method is desirable from the point of view of coverage.
Next, as shown in
FIG. 19
, an etch back for flattening is carried out so as to remove metal
110
, other than the portion which has been filled in and a metal
111
is formed. This etch back method uses conventional dry etching, CMP (chemical mechanical polishing), or the like.
Next, as shown in
FIG. 20
, etching off of silicon oxide film
108
is carried out. This etching off is possible by means of conventional wet etching and dry etching may be used at the same time. At this point in time, a pillar-type capacitor lower electrode
112
is formed in a self-aligning manner with respect to metal
111
. By using such a formation method, the entirety is in a form of being covered with silicon nitride film
107
, other than on the portion where capacitor lower electrode
112
and contact plug
106
make contact where each other and, therefore, a misalignment, if any, will not effect subsequent steps.
Next, as shown in
FIG. 21
, a side wall film is formed by using the pillar of a damascene pillar-type cell as a core. Side wall film
112
may be made of the same material as the core or may be of a different material. Here, in some cases, this process may be omitted. The thickness of side wall film
112
is, in general, several tens of nm of the thickness of the flat portion. Concretely, the formation of the side wall film is possible by carrying out an etch back for the entire surface after depositing a material for capacitor lower electrode
112
. According to this method, the top surface of the capacitor lower electrode may be lost but, even if so, no problems arise concerning the performance of the capacitor.
Next, as shown in
FIG. 22
, capacitor dielectric film
113
is formed. The film thickness is from approximately several nm to several tens of nm. Next, capacitor upper electrode
114
of which the film thickness is approximately several tens of nm is formed on capacitor dielectric film
113
. After this, the formation of a conventional interlayer insulating film and an aluminum wiring process are carried out and, thereby, a capacitor having a damascene pillar-type cell is formed. Here, unnecessary portions of capacitor upper electrode
114
are capacitor dielectric film
113
are removed through etching, or the like, so as to complete a capacitor of a structure as shown in FIG.
13
.
In a capacitor having a damascene pillar-type cell of the above described structure, when the film thickness of the dielectric film is reduced together with the scaling down of the design rule, the dielectric constant is lowered so as to so that the capacitance of the capacitor is lowered. In this damascene pillar structure, it is necessary to make the thickness of the dielectric film thin in order to sufficiently cover the cell with the cell plate when the design rule is scaled down to approximately 0.10 &mgr;m. However, in a crystallized dielectric such as a perovskite dielectric film the dielectric constant is often lowered when the film thickness is made thinner (to 10 nm). This is because a high dielectric constant occurs due to displacement of Ti atoms in the crystal lattice and because the crystal structure is affected and the crystal lattice is disturbed when the film thickness becomes smaller. Therefore, even in the case that the film thickness is made thinner, an increase of a leak current occurs instead of the increase in the capacitance of the capacitor.
FIG. 23
shows the mutual relationship between the actual film thickness and the film thickness as converted to oxide film teq as an example of the occurrence of the above leak current. As can be seen from a graph shown in this
FIG. 23
, the smaller the film thickness of capacitor dielectric film
113
becomes, the smaller becomes the degree of reduction of the film thickness as converted to oxide film teq, that is to say, in the conventional structure of a damascene pillar-type cell, the greater is the miniaturization of the capacitor, the further the capacitance of the capacitor is lowered.
SUMMARY OF THE INVENTION
A purpose of the present invention is to provide a semiconductor device which includes a capacitor wherein the capacitance of the capacitor can
McDermott & Will & Emery
Renesas Technology Corp.
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