Shared memory architecture for increased bandwidth in a...

Details Shared memory architecture for increased bandwidth in a... Shared memory architecture for increased bandwidth in a...

2002-07-24

2004-06-22

Fleming, Fritz (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S023000, C710S027000, C347S005000

Reexamination Certificate

active

06754733

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of the invention is printer controllers.
BACKGROUND OF THE INVENTION
Printer controllers for computer systems have steadily grown in sophistication and performance. Digital signal processors are increasingly used to perform the wide variety of tasks required which include a high level of signal processing capability and multi-faceted interface requirements. Memory control is centralized in a memory interface controller function. These systems use increasingly large memory functions of several types, such as synchronous DRAM (SDRAM) and flash memory.
FIG. 1
illustrates the prior art steps required to process the input data that a printer typically receives from a conventional personal computer (PC). The output from the PC normally is supplied by a printer driver
101
that prepares an output print file. This file includes a set of instructions and data in a page description language (PDL) or compressed bitmap format. These instructions and data may be transported to the printer via IEEE 1284 (Firewire) or Universal Serial Bus (USB) cabling or over a local area network and stored in an input buffer memory
102
.
The first computational step in the printer controller pipeline is interpretation
103
of the data. The display list from interpretation
103
includes a description of individual elements of graphics data or text data along with the position of these elements on the page. The display list may be in a banded or a non-banded format. In a banded format discrete bands are defined and formed as a part of the processing. After rendering, a number of these bands collectively form a full printer controller output page. In a non-banded format, each page is interpreted as a unit. After rendering, this unit forms an integral part of printer controller output.
The rendering pipeline stage
104
reduces the interpreted data of the display list to printer specific raster data. This process is sometimes called rasterization. The output of the rendering process is a bit map format in which discrete digitized dots (pixels) are generated to control the output device (e.g. ink jet pen, laser drum) with proportions of the colors cyan, yellow, magenta, and black. The rendering step is well suited to digital processing operations commonly used in digital signal processor devices. After rendering, the bit map data is stored in an output buffer memory stage
105
. This bit map data is sent as needed to the printer output mechanism
106
.
FIG. 2
illustrates a high-level view of the full complement of printer pipeline functions of the prior art. The input data has a variety of sources, such as spooled jobs on disc
201
, parallel printer port
202
, Universal Serial Bus (USB) port
203
, Ethernet TCP/IP port
204
and IEEE 1284 (Firewire)
205
. Each data source has its specific data format. This data must be reduced to a common format for processing in the pipeline. Streams interface unit
207
adjusts the format of the input data as required. For example, data arrives in parallel form from parallel printer port
202
and is converted in streams interface unit
207
as necessary for uniform processing in later stages. Likewise, streams interface unit
207
often carries out format adjustments upon data from USB port
203
in queue coming from the host processor.
Streams interface unit
207
sends data to the path that performs parallel interpretation of the composite postscript
208
, printer control language PCL
210
or other PDL interpreter
210
. Page pipeline block
209
re-assembles the results of the interpretation process into page format for page oriented processing before submitting page data to rendering unit
212
. Postscript interpreter
208
or PCL interpreter
210
may send banded format data directly to rendering unit
212
. Rendering unit
212
also performs compression, decompression or screening as required. PDL print controller to print engine controller interface unit
225
supplies data and control information to ASIC special purpose processor
213
to drive paper path control
216
, the control panel/display
214
and the video data output
215
.
FIG. 3
illustrates a conventional printer controller system. The system has typically a main processor
300
and a system ASIC printer controller
301
, both served by a single processor bus
302
. All major compute functions are carried out within the main processor
300
.
The system interfacing to a personal computer (PC)
303
is directed by the system ASIC printer controller
301
via a USB port
304
or alternately by an IEEE 1284 (Firewire) compatible parallel port
305
. ASIC printer controller
301
directs networking by the system via the Ethernet
306
from a local area network
307
and provides a mass storage interface via an ATA-4 compatible disc interface
308
to disc drive
309
.
System data movement among main processor
300
, system ASIC print controller
301
, DRAM memory
310
and FLASH or ROM memory
311
are all accomplished via processor bus
302
. System ASIC print controller
301
provides interface to printer engine via engine control signals
312
and video data output
313
.
FIG. 4
illustrates the memory bandwidth requirement for the processor-initiated video output in the conventional system of FIG.
3
. The processor-initiated video output is the most bandwidth intensive operation and must occur in real time. Three operations require processor bus
302
bandwidth: processor band clearing and write
406
of rasterized data to the output band buffer; the real-time read
407
of data from the printer engine; and real-time write
408
of data to the printer engine. This video output requires a total of 256 Mbytes/page for processor band clearing and write
406
, 128 Mbytes/page for real-time read
407
and 128 Mbytes/page for real-time write
408
for a total of 512 Mbytes/page of processor bus
302
bandwidth. This translates into 136 Mbytes/sec for a 16 page/min printer.
FIG. 5
illustrates the data flow diagram for a conventional printer controller using a single processor bus. Three parts of the printer controller are identified with dashed-line boxes: DRAM
550
, processor
551
, and engine and peripheral interfaces
552
. Operations and operation end points given in boxes in
FIG. 5
require in many cases that the main processor yield the main processor bus to non-compute operations thereby slowing down overall processing speed. Each transfer of data is represented by a line and is labeled with the transfer size in Mbytes/page. Note that all transfer size requirements in
FIG. 5
involve use of bus bandwidth on the common processor bus
302
in FIG.
3
. Table 1 gives a complete list of the bus bandwidth requirements for each major controller operation. Specific operations in
FIG. 5
may be cross-referenced to the list given following Table 1, which also shows the bus bandwidth requirements for each major controller operation.
TABLE 1
Processor Bus
Number
Operation
Mbytes/page
1
Networking
120
2
Spooling
80
3
Stream I/F
80
4
Image Filter
80
5
Color Conversion
47
6
Text Interpretation
4
(Font Decompression)
7
Graphics Interpretation
64
(Display List)
8
Band Clearing
128
9
Rendering and Compression
43
10
Compressed Output Data
11
11
Decompress and Screen
139
12
Video Output Data
256
Total
1052
These data paths are detailed below. Note: DMA is direct memory access; PCI
1. Networking: Processor Bus 120 Mbytes/page
From PDL input
500
to DMA
531
to PCI buffer
501
to DMA
521
to mbuffer
502
to DMA
522
to socket buffer
503
.
2. Spooling: Processor Bus 80 Mbytes/page
From socket buffer
503
to DMA
523
to temporary buffer
504
to DMA
524
to DOS buffer
505
to DMA
532
to disc write DMA
506
.
3. Stream I/F: Processor Bus 80 Mbytes/page
From disk read DMA
507
to DMA
533
to DOS buffer
508
to DMA
525
to stream buffer
510
.
4. Image Filter: Processor Bus 80 Mbytes/page
From stream buffer
510
to DMA
526
to temporary buffer
511
to filter
512
to image buffer
513
.
5. Color Conversion: Processor Bus 47 Mbytes/page
From

Affiliated with

Also associated with

Rating

Shared memory architecture for increased bandwidth in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shared memory architecture for increased bandwidth in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shared memory architecture for increased bandwidth in a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3341569