Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2001-08-03
2004-06-22
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S033000
Reexamination Certificate
active
06754732
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to a system and method for efficiently performing direct memory access operations, and in specific to a method and system that utilizes an enhanced direct memory access controller to perform both a desired data transfer operation and one or more data queue directory updates to properly reflect such desired data transfer.
BACKGROUND
Computer systems are heavily relied on today for performing a variety of tasks. Such computer systems are often required to handle data in some manner. For example, data is often transferred from one memory location (or address) to another memory location (or address). For instance, data may be transferred from one device to another device, from one device to memory, from a software application to a device, from a software application to memory, etcetera. Computer systems generally include at least one central processing unit (CPU or processor), which acts as the electronic “brain” of a computer device. As is well known, the CPU is responsible for performing most calculations/instructions, and is often relied on for performing a transfer of data from one memory location to another memory location. In early computer systems, the CPU was responsible not only for the execution of programs, but was also responsible for transferring data to and from various memory locations (e.g., transferring data to and from peripheral devices, etcetera). For instance, the CPU typically operates on data stored in a main memory. Because there are practical size limitations on such main memory, bulk memory storage devices may be provided in addition to and separately from the main memory. When the CPU wants to make use of data stored in such a bulk storage device, such as a hard disk, for example, the data is typically moved from the hard disk into the main memory.
Utilizing the CPU to perform such data transfers is very inefficient because such data transfers prevent the CPU from performing other tasks, thereby hindering the overall efficiency of the computer system. Accordingly, direct memory access (DMA) is commonly utilized to enable computer systems to cut out the “middle man,” thereby allowing the CPU to perform other tasks. For example, a DMA chip (or DMA controller) is commonly included in computer systems to enable a peripheral device to effectively transfer data itself, leading to increased performance of the computer system. Prior art DMA systems and methods are well known by those of ordinary skill in the art, and therefore will only briefly be described hereafter.
DMA circuitry generally provides “channels,” along with circuitry to control such channels, which allow the transfer of data without the CPU controlling every aspect of the transfer. Such circuitry is commonly part of the system chipset on the motherboard of a personal computer (PC), for example. When a device desires to move a block of data, the DMA controller receives descriptor information from the CPU as to the base location from where bytes are to be moved (i.e., the “source address”), the address to where the bytes should be moved (i.e., the “destination address”), and the number of bytes to move (i.e., the “length” of the block of data). Once it receives such descriptor information, the DMA controller oversees the transfer of the data within the computer system. Once the data move is complete, the DMA controller notifies the CPU of such completion. Normally, DMA operations are used to move data between input/output (I/O) devices and memory.
Turning to
FIG. 1
, a relatively simple example of a data move operation performed by a DMA is shown. As shown, a computer system
100
includes a first memory location
102
and a second memory location
104
. For example, memory location
102
may be included within a hard disk or some other type of peripheral device, and memory location
104
may be the main memory of computer system
100
. When a device or an application desires to transfer a block of data from memory location
102
to memory location
104
, CPU
114
provides to DMA
106
the necessary descriptor information for identifying the desired transfer. That is, CPU
114
provides descriptor information that includes the source address
108
(i.e., the base address from where bytes are to be moved), the destination address
112
(i.e., the address to where the bytes should be moved), and the length
110
of the block of data to be moved. Based on the received descriptor information, DMA
106
performs the identified data transfer operation from memory location
102
to memory location
104
. Once complete, DMA
106
notifies CPU
114
of the completion of the requested data transfer operation.
DMA
106
in
FIG. 1
may be referred to as a “simple DMA,” in that it performs a data transfer that is identifiable by a single descriptor (e.g., a single source, destination, and length). However, a more complex DMA, which may be referred to as a “chaining DMA” is also available in the prior art. Such a chaining DMA is capable of performing a data transfer of a block of data that is not identifiable by a single descriptor. Turning to
FIG. 2
, an example of a data move operation that requires multiple descriptors for identification to be performed by a chaining DMA is shown. As shown, a computer system
200
includes a first memory location
202
and a second memory location
204
, similar to that of
FIG. 1
described above. For example, memory location
202
may be included within a hard disk or some other type of peripheral device, and memory location
204
may be the main memory of computer system
200
. A device or application may desire to transfer data, which such device or application logically views as a block
208
. That is, data may be treated as a logical “block”
208
by an application and/or device, but such logical block
208
may not actually be a contiguous block within the physical memory. As shown in the example of
FIG. 2
, logical block
208
is actually divided among three separate memory locations (or sub-blocks)
210
A
,
210
B
, and
210
C
within first memory location
202
. That is, logical block
208
comprises three separate source addresses
210
A
,
210
B
, and
210
C
.
Furthermore, each source address may have a different length. That is, the portion of data block
208
starting at source address
210
A
may include contiguous data having length
211
A
, the portion of data block
208
starting at source address
210
B
may include contiguous data having length
211
B
, and the portion of data block
208
starting at source address
210
C
may include contiguous data having length
211
C
, wherein lengths
211
A
,
211
B
, and
211
C
may be different. Additionally, each sub-block
210
A
,
210
B
, and
210
C
must have a different destination address. Otherwise, one sub-block would overwrite all or a portion of another of the sub-blocks. For example, if sub-blocks
210
A
,
210
B
, and
210
C
were all written to the exact same destination address, the latter sub-blocks to be written to such destination address would overwrite all or a portion (depending on the length of each sub-block) of the earlier written sub-blocks. Thus, multiple descriptors are required to identify the data transfer operation of logical block
208
. More specifically, three separate source addresses, three separate destination addresses, and three separate lengths are required to identify the data transfer of block
208
from memory
202
to memory
204
.
Accordingly, when a device or an application desires to transfer block
208
from memory location
202
to memory location
204
, CPU
214
provides to DMA
206
the multiple descriptors necessary to identify such a data transfer. The multiple descriptors are referred to as being “chained” together because the DMA
206
must complete all of the multiple data transfers before indicating to CPU
214
that the transfer of block
208
is complete. Thus, in the example of
FIG. 2
, DMA
206
will receive the three chained descriptors and perform the necessary operations to move the data of
Dixon Huey P.
El-Khoury Roland
Hankins Steve L.
Chen Alan
Fulbright & Jaworski LLP
Gaffin Jeffrey
Intervoice Limited Partnership
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