Trench cell for a DRAM cell array

Details Trench cell for a DRAM cell array Trench cell for a DRAM cell array

2003-03-24

2004-11-23

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000

Reexamination Certificate

active

06822281

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a trench cell for storing digital information in a DRAM structure and to a cell array constructed from such trench cells.
DRAM arrays are, typically, realized by a regular configuration of trench cells. For such a purpose, a multiplicity of trench holes is etched into a semiconductor substrate. The lower region of a trench hole, then, serves in each case for accommodating a storage capacitor of the DRAM cell. One or a plurality of selection transistors, embodied as field-effect transistors, is provided per memory cell. The gates of the field-effect transistors can be driven through a word line associated with the cell. Through the source/drain path of the selection transistors, the storage capacitor can be connected to an associated bit line to write digital information to the cell or to read stored values from the cell.
In the course of advancing miniaturization, it becomes more and more important to construct memory cells in a manner that saves as much space as possible. For such a purpose, it is known to integrate the selection transistor or selection transistors of a trench cell into the sidewall of the trench hole. In the case of such vertical selection transistors, the gate electrode of the selection transistor is integrated into the upper part of the trench hole. A thin oxide layer at the sidewall of the trench hole serves as gate oxide. The lower source/drain terminal is formed by a buried doping region, the so-called “buried strap”, which is conductively connected to the storage capacitor. A doping region near the surface forms the upper source/drain terminal.
The prior art discloses trench cells for DRAM arrays as a so-called VTC cell concept, in which two vertical selection transistors disposed opposite one another are provided per trench cell. Such a trench cell is shown in FIG.
1
. In this cell, the usually weakly p-doped silicon substrate is contact-connected in the necessary manner from the lower substrate region, to be precise, usually from outside the cell array. Because the doping density of the substrate must not be too high, only a contact-connection with relatively low conductivity can be implemented. Furthermore, the problem occurs that the substrate region above the n
+
-doped buried doping regions can be pinched off from the lower substrate region by the relatively greatly extended space charge zones of the doping regions. This, then, has the effect that the substrate potential for the vertical selection transistors floats freely and erroneous switching states of the transistors arise on account of these fluctuations. In the case of the trench cell shown in
FIG. 1
, such a pinch-off problem has only been able to be combated hitherto by the cells not being disposed too closely in their spacing from one another. More extensive miniaturization is prevented as a result.
FIG. 2
shows a further trench cell type referred to as a hybrid cell concept. In such a hybrid cell, only one vertical selection transistor is provided per trench cell. In this cell type, too, the substrate is contact-connected from the lower substrate region. The problem with this cell type is that a parasitic transistor can form on the side of the cell opposite to the selection transistor, which has the effect that disturbing leakage currents occur. To prevent these leakage currents from becoming too large, it has always been necessary hitherto to ensure that the cells are not disposed too close together. More extensive miniaturization is prevented as a result.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a trench cell for a DRAM cell array that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that provides a trench cell that enables a densely packed configuration of the trench cells without the process of reading in and out being impaired by leakage currents, and at the same time, enables the semiconductor substrate to be reliably contact-connected.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a trench cell for storing digital information, including a semiconductor substrate of a first conductivity type, the semiconductor substrate defining a trench hole having a lower region, a surface, and an upper region with a sidewall section, a storage capacitor being formed in the semiconductor substrate in the lower region of the trench hole, the storage capacitor having an inner electrode, a dielectric intermediate layer, and an outer electrode, a vertical selection transistor being formed in the semiconductor substrate in the upper region of the trench hole at the sidewall section, the vertical selection transistor having an upper source/drain doping region and a lower source/drain doping region of a second conductivity type, a gate electrode, an insulator layer, and a channel region being disposed between the upper source/drain doping region and the lower source/drain doping region, the channel region being isolated from the gate electrode by the insulator layer, a bit line running in a direction perpendicular to the trench hole, the bit line being connected to the upper source/drain doping region, a word line running perpendicular to the trench hole and transverse with respect to the bit line, the word line being connected to the gate electrode, the lower source/drain doping region being connected to one of the inner and outer electrodes, and a doping region of the first conductivity type being adjacent the surface, the doping region being disposed in the semiconductor substrate opposite the vertical selection transistor viewed in the direction of the bit line adjacent to the sidewall section of the trench hole. In other words, the doping region is disposed adjacent the sidewall section of the trench hole in the semiconductor substrate opposite the vertical selection transistor viewed in the direction of the bit line.
With the objects of the invention in view, there is also provided a cell array, including a multiplicity of regularly disposed trench cells according to the invention.
The invention's trench cell for storing digital information in a DRAM structure has a vertical selection transistor disposed on the—seen in a bit line direction—first side of the trench hole provided for the trench cell. The upper source/drain terminal of the vertical selection transistor is formed by a doping region situated beside the trench hole and the lower source/drain terminal of the vertical selection transistor is formed by a buried doping region. Both doping regions have a doping of a first conductivity type. The trench cell has a doping region near the surface, of a second conductivity type, on the—seen in the bit line direction—second side adjacent to the trench hole.
The aforesaid leakage current that has been able to cause considerable disturbance to the read-in and read-out behavior of the vertical selection transistors can be, effectively, suppressed by the invention's doping region near the surface, of the opposite conductivity type to the source/drain doping. This additional blocking doping region is disposed adjacent to a trench sidewall oxide of the cell considered and prevents a parasitic transistor from being able to form at the rear wall of the cell considered. A conductive channel cannot then form between the blocking doping region and the buried source/drain doping region of the selection transistor of the adjacent cell. Independently of the charge of the gate electrode associated with the transistor considered, this prevents a leakage current from being able to form.
In accordance with another feature of the invention, it is advantageous if the blocking doping region extends as far as the substrate surface and is highly doped. This is because the doping implantation can be performed from the substrate surface in such a case. It is furthermore advantageous here if, above the blocking doping region, an interconnect is disposed on the substrate surface,

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