Three input field programmable gate array logic circuit...

Details Three input field programmable gate array logic circuit... Three input field programmable gate array logic circuit...

2002-05-01

2004-08-17

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S041000

Reexamination Certificate

active

06777977

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to programmable integrated circuits. More particularly, the present invention relates to a programmable logic circuit and architecture for use in integrated circuits, such as field programmable gate array (FPGA) integrated circuits.
2. Background
A field-programmable gate array (FPGA) is an integrated circuit (IC) that includes an array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. Programmable buses link the cells to one another. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing Boolean functions of multiple variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain a plurality of flip-flops. Two types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
Recent advances in user-programmable interconnect technology have resulted in the development of FPGAs which may be customized by a user to perform a wide variety of combinatorial and sequential logic functions. Numerous architectures for such integrated circuits are known. Examples of such architectures are found disclosed in U.S. Pat. No. 4,870,302 to Freeman, U.S. Pat. No. 4,758,745 to El Gamal et al., and U.S. Pat. No. 5,132,571 to McCollum et al. The architecture employed in a particular FPGA integrated circuit will determine the richness and density of the possible interconnections that can be made among the various circuit elements disposed on the integrated circuit and thus profoundly affect its usefulness.
While these circuits provide a degree of flexibility to the designer of user-programmable logic arrays, there is always a need for improvement of functionality of such circuits. In a typical logic cell with three input variables, there are at least seventy-eight potential functions resulting in different outputs. In addition, for each of the seventy-eight functions there are inverse functions created by inverting all data input lines. However, no one logic cell has been able to implement all seventy-eight potential functions. For instance, a prior art logic cell could implement a flip-flop, latch, or other three input function but not all three input logic functions, such as a three-input exclusive-OR or majority function (a function whose output represents the majority of the bits input).
BRIEF DESCRIPTION OF THE INVENTION
The present invention relates to FPGA architectures, and more specifically to the core architecture of an FPGA integrated circuit including the functional circuit modules, sometimes referred to as programmable logic modules, and the interconnect architecture which is used to define the programmable logic modules.
The present invention includes a logic cell including a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential units including a flip-flop.


REFERENCES:
patent: 4706216 (1987-11-01), Carter
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4870302 (1989-09-01), Freeman
patent: 5132571 (1992-07-01), McCollum et al.
patent: 5451887 (1995-09-01), El-Avat et al.
patent: 5570041 (1996-10-01), El-Avat et al.
patent: 5999015 (1999-12-01), Cliff et al.
patent: 6271680 (2001-08-01), Mendel et al.

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