User equipment (UE) having a hybrid parallel/serial bus...

Details User equipment (UE) having a hybrid parallel/serial bus... User equipment (UE) having a hybrid parallel/serial bus...

2002-02-22

2004-11-23

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C365S189011, C365S189040, C365S230030, C365S230060, C365S230080

Reexamination Certificate

active

06823469

ABSTRACT:

BACKGROUND
The invention relates to bus data transfers. In particular, the invention relates to reducing the number of lines used to transfer bus data.
One example of a bus used to transfer data is shown in FIG.
1
.
FIG. 1
is an illustration of a receive and transmit gain controllers (GCs)
30
,
32
and a GC controller
38
for use in a wireless communication system. A communication station, such as a base station or user equipment, transmits (TX) and receives (RX) signals. To control the gain of these signals, to be within the operating ranges of other reception/transmission components, the GCs
30
,
32
adjust the gain on the RX and TX signals.
To control the gain parameters for the GCs
30
,
32
, a GC controller
38
is used. As shown in
FIG. 1
, the GC controller
38
uses a power control bus, such as a sixteen line bus
34
,
36
, to send a gain value for the TX
36
and RX
34
signals, such as eight lines for each. Although the power control bus lines
34
,
36
allow for a fast data transfer, it requires either many pins on the GCs
30
,
32
and the GC controller
38
or many connections between the GCs
30
,
32
and GC controller
38
on an integrated circuit (IC), such as an application specific IC (ASIC). Increasing the number of pins requires additional circuit board space and connections. Increasing IC connections uses valuable IC space. The large number of pins or connections may increase the cost of a bus depending on the implementation.
Accordingly, it is desirable to have other data transfer approaches.
SUMMARY
A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.


REFERENCES:
patent: 5327126 (1994-07-01), Beanland
patent: 5400369 (1995-03-01), Ikemura
patent: 5526360 (1996-06-01), Kraft
patent: 5541596 (1996-07-01), Yoshida
patent: 5602780 (1997-02-01), Diem et al.
patent: 5847578 (1998-12-01), Noakes et al.
patent: 5926120 (1999-07-01), Swenson et al.
patent: 6040792 (2000-03-01), Watson et al.
patent: 6122683 (2000-09-01), Ku et al.
patent: 6128244 (2000-10-01), Thompson et al.
patent: 6134247 (2000-10-01), Solana de Quesada et al.
patent: 42847 (1991-04-01), None

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