Insulated gate semiconductor device for realizing low gate...

Details Insulated gate semiconductor device for realizing low gate... Insulated gate semiconductor device for realizing low gate...

2002-07-30

2004-08-24

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S329000, C257S331000, C257S341000, C257S342000

Reexamination Certificate

active

06781200

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulated gate semiconductor device and, more particularly, to an improvement of an insulated gate bipolar transistor and a power MOSFET having an insulated gate, which realizes a low gate capacity and a low short-circuit current at a low resistance, and to a method of manufacturing the insulated gate bipolar transistor.
2. Description of the Prior Art
In general power electronics for driving a motor and the like, power semiconductor elements of, for example, an insulated gate bipolar transistor (to be referred to as “IGBT” hereinafter) are mainly used as switching elements because of their characteristics in a region having a rated voltage of 300 V or more. Of these power semiconductor elements, there attract increasing attentions to an insulated gate semiconductor device having a trench gate, i.e., an insulated gate semiconductor device having a structure in which a gate electrode is buried in a trench formed in one major surface of a semiconductor substrate because of the following advantages. That is, the insulated gate semiconductor device can be easily micropatterned and integrated at a high density.
FIG. 6
is a sectional view showing an example of a structure of a conventional trench gate IGBT (to be referred to as “TIGBT” hereinafter) An example of a typical TIGBT configuration is shown in
FIG. 7A
as an upper plan view thereof, and in
FIGS. 7B and 7C
as sectional views taken on lines A-A′ and B-B′ in
FIG. 7A
, respectively. The structure and operation of the conventional TIGBT will be briefly described below with reference to FIG.
6
and
FIGS. 7A
to
7
C.
In the illustrated configuration, an n
+
-type buffer layer
102
is formed on a p
+
-type substrate
101
, and a collector electrode
112
is formed on the lower surface of the p
+
-type substrate
101
. An n
−
-type semiconductor layer (referred to as “base layer”)
103
is formed on the n
+
-type buffer layer
102
. Furthermore, in a cell region of the TIGBT, a p-type base region
104
is selectively formed by diffusing a p-type impurity on the upper surface of the n
−
-type base layer
103
. In a part or the entire area of the upper surface of the p-type base region
104
, an n
+
-type emitter region
105
is formed by selectively diffusing a high concentrated n-type impurity.
In this conventional configuration, a plurality of trenches
107
are formed to extend to cross the n
+
-type emitter region
105
, and are arranged at predetermined intervals (i.e., pitches) W in parallel to each other. Each trench is formed to have such a depth that the trench extends from the level of the n
+
-type emitter region
105
to the n
−
-type base layer
103
. A trench gate electrode
110
(
110
a
,
110
b
and
110
c
) of the MOS transistor is buried in each of the trenches
107
through a gate insulating film
108
. The p-type base region
104
opposing the gate electrode
110
and interposed between the n
+
-type emitter region
105
and the n
−
-type base layer
103
functions as a channel region.
The upper surface of the trench gate electrode
110
and a part of the upper surface of the n
+
-type emitter region
105
are coated with an insulating interlayer
109
, and an emitter electrode
111
is formed to cover a part of the upper surface of the n
+
-type emitter region
105
and the entire upper surface of the insulating interlayer
109
. Also, as shown in
FIG. 6
, a p-type semiconductor layer
113
for keeping a withstand voltage high is formed in a region immediately below a gate wiring layer GL.
FIGS. 8A
,
8
B, and
8
C show a typical structure of a conventional carrier stored trench-gate bipolar transistor (to be referred to as “CSTBT” hereinafter) to improve the characteristics of the TIGBT shown in
FIGS. 7A-7C
, where
FIG. 8A
is an upper plan view thereof and
FIGS. 8B and 8C
are sectional views taken on lines A-A′ and B-B′ in
FIG. 8A
, respectively. This improved TIGBT structure is different from the old TIGBT structure in
FIGS. 7A
,
7
B, and
7
C in that an n
−
-type semiconductor layer (i.e., carrier stored region)
113
for storing carriers is interposed between the p-type base region
104
and the n
−
-type base layer
103
.
The operation of the conventional IGBT will be described below with reference to
FIGS. 7A
to
7
C and
FIGS. 8A
to
8
C. In each of the structures shown in the
FIGS. 7A
to
7
C and
FIGS. 8A
to
8
C, while a predetermined positive collector voltage V
CE
is applied across the emitter electrode
111
and the collector electrode
112
, a predetermined positive gate voltage V
GE
is applied across the emitter electrode
111
and the trench gate electrode
110
to turn on the gate.
At this time, the type of the channel region is inverted from a p type to an n type to form a channel, and electrons are moved from the emitter electrode
111
and implanted into the n
−
-type base layer
103
. The implanted electrons set the region between the p
+
-type substrate
101
and the n
−
-type base layer
103
in a forward bias state. Implantation of carrier holes from the p
+
-type substrate
101
considerably decreases the resistance of the n
−
-type base layer
103
and increases the current capacity of the IGBT. In this manner, implantation of holes from the p
+
-type substrate
101
in the IGBT decreases the resistance of the n
−
-type semiconductor layer
103
.
An operation performed when the IGBT is turned off will be described below. In the structures
FIGS. 7A
to
7
C and
FIGS. 8A
to
8
C, the gate voltage V
GE
applied across the emitter electrode
111
and the trench gate electrode
110
in the ON state is set to zero or negative (inverted vias) More specifically, when the gate is turned off, the channel region having its conductivity type inverted into an n type is returned to a p-type region, and the implantation of electrons from the emitter electrode
111
into the n
−
-type base layer
103
is stopped. The stop of implantation of electrons causes the implantation of holes from the p
+
-type substrate
101
to be stopped. Thereafter, the electrons and holes stored in the n
−
-type base layer
103
(and the n
+
-type buffer layer
102
) are collected into the collector electrode
112
and the emitter electrode
111
, or are combined to each other again to disappear.
The characteristics of the TIGBT shown in
FIGS. 7A
to
7
C can be improved compared to a plane gate IGBT because MOS transistors on the upper surface of the TIGBT can be micropatterned to have a size which is about {fraction (1/10)} the size of the MOS transistors of a plane gate IGBT. In the plane gate IGBT, a current path is formed in a region sandwiched by a p-type base layer on the upper surface, and a voltage drop in this region is large. However, in the above-described TIGBT, the gate
110
is formed to penetrate the p-type base region
104
. For this reason, the current path has no region surrounded by the p-type base layer, so that the characteristics can be improved.
In the CSTBT shown in
FIGS. 8A
to
8
C, the n
−
-type semiconductor layer (carrier stored region)
113
for storing carriers is formed on the lower surface of the p-type base region
104
. For this reason, holes from the p
+
-type substrate
101
are prevented from passing through the emitter electrode
111
, and the holes are stored in the carrier stored region
113
located on the lower surface of the p-type base region
104
. Therefore, ON voltage can be decreased to a voltage which is lower than that of the TIGBT.
However, in the conventional TIGBT shown in
FIGS. 7A
to
7
C, since the cell size is reduced to a size which is about {fraction (1/10)} the cell size of a plane gate, the ON voltage can be considerably reduced advantageously, but a gate capacity and a short-circuit current increase disadvantageously. In order to solve the problem, the pitches u

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