Double data rate scheme for data output

Details Double data rate scheme for data output Double data rate scheme for data output

1999-09-02

2004-02-17

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S104000, C711S105000, C711S167000, C711S157000, C710S007000, C710S020000, C710S021000, C710S060000

Reexamination Certificate

active

06694416

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to memory devices, and more particularly to dynamic memory.
BACKGROUND OF THE INVENTION
Memory circuits are vital components in computer and electronic systems which require permanent or temporary data storage. The memory circuits, such as dynamic random access memory (DRAM), are used in computer systems such as a processor system.
In processor based systems and electronic systems, the system operates at a certain frequency. Ideally, memory devices would operate at the same frequency as the system. However, memory devices do not generally operate at the same speed as the system. This is due to the high cost involved in manufacturing and operating memory devices that can operate at very high frequencies. Memory devices generally operate at a fraction of the speed of the processor and cause the system to run slower.
Memory devices have been unable to operate at the speed of microprocessors because of how they operate. Memory devices have to be very compact to hold and access the large amounts of data they are required to hold. For these devices to operate faster, a significant cost must be incurred to design and produce these devices. Generally, the cost prohibits the inclusion of faster memory devices in these systems.
In these computer and electronic systems, operational speeds of dynamic random access memories used as main memories have been increased, but are still low compared with operation speeds of microprocessors. This relatively low speed increases a wait time of the microprocessor, and impedes fast processing, as an access time and a cycle time of the DRAM form a bottleneck in a whole system performance.
One way that memory circuits can be made to write and read data faster is to build the memory circuits so they operate at a higher clock frequency. This has been done in microprocessors as can be seen by the increase in operating frequency in microprocessors. For example, a microprocessor running at 200 Mhz is generally much faster than a microprocessor running at 50 Mhz. However, by operating circuits at higher operating frequency, additional problems are encountered. For example, the amount of heat produced and power used by a circuit operating at a higher frequency can be greatly increased. This corresponds to high cost solutions to handle the heat and power problems. Furthermore, the increased use of portable devices, such as laptop computers, requires that power use by circuits be reduced. Also, the higher operating frequency can cause integrated circuit die to be more expensive.
Since memory devices are used in many different systems, increasing the speed of memory devices without significantly increasing the cost of memory devices can allow everything from wordprocessors to automatic teller machines to perform their tasks quicker.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for double data rate device and methods of reading data at double data rates.
SUMMARY OF THE INVENTION
One embodiment of the present invention is a double data rate memory device. The double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to output data from the storage unit on rising and falling edges of an external clock signal. Another embodiment is a memory device. The memory device includes a storage element and a plurality of pipelines. Each of the plurality of pipelines passes data on a plurality of events.


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