Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-06
2004-06-01
Pert, Evan (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S217000
Reexamination Certificate
active
06744103
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of metal oxide semiconductor field effect transistors (MOSFETs), and has specific application to the fabrication of these devices in the context of an integrated circuit (IC).
Since the invention of the transistor in the late 1940s, tremendous advances have been made in the field of microelectronics. Current technology allows for the cost-effective fabrication of integrated circuits (ICs) with over 100 million components—all on a piece of silicon roughly 10 mm on a side. The one billion transistor IC will be commercially available within a few years. The desire for greater functionality and performance at less cost per IC drives several trends.
First, functionality drives IC transistor counts up. Second, the transistors themselves are being reduced in size so as to achieve greater packing density and, very importantly, to improve their performance. As far as performance is concerned, the key parameter for Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFETs, the dominant transistor technology of the day) is the channel length. The channel length (L) is the distance that charge carriers must travel to pass through the device, and a reduction in this length simultaneously implies higher current drives, reduced parasitic resistances and capacitances and improved high-frequency performance. A common figure-of-merit is the power-delay product, and this generalized measure of transistor performance improves as the cube of the inverse of the channel length (1/L
3
). This explains the tremendous incentive that IC manufacturers have to reduce the channel length as much as manufacturing capabilities will allow.
For digital applications, MOS transistors behave like switches. When “on,” they drive relatively large amounts of current, and when turned “off” they are characterized by a certain amount of leakage current. As channel lengths are reduced, drive currents increase, which is beneficial for circuit performance as stated above. However, leakage currents increase as well. Leaky transistors contribute to quiescent power dissipation (the power dissipated by an IC when idle) and in extreme cases can affect the transfer of binary information during active operation. Device designers therefore have good reason to keep leakage currents low as channel lengths are reduced.
MOS transistor leakage currents are traditionally controlled by introducing controlled amounts of impurities (dopants) into the channel region of the device, and by tailoring the source/drain lateral and vertical doping distributions. Although these approaches are effective in shoring up the potential barrier internal to the MOS transistor and therefore reducing the leakage current, they can also contribute to degraded drive current and increased parasitic capacitance—the very items that channel length reduction is meant to improve. Furthermore, depending on exactly how in the manufacturing process the channel and tailored source/drain dopants are introduced, the manufacturing cost can be affected significantly. Given traditional MOS transistor design and architecture, there are only limited solutions to the trade-off between drive current, leakage current, parasitic capacitance and resistance, and manufacturing complexity/cost.
The present invention offers a new relationship between these competing requirements, and makes possible MOS devices with characteristics that are not achievable with traditional (impurity doped) MOS architectures. The use of metal for the source and drain and a simple, uniformly implanted channel dopant profile provides for improvements to device characteristics in terms of reduced parasitic capacitance, reduced statistical variations in these characteristics (especially as the channel length is decreased) and reduced manufacturing cost and complexity.
DESCRIPTION OF THE PRIOR ART
Doping Profiles
Previous generations of MOS transistors have relied on laterally uniform, and vertically non-uniform channel doping profiles to control drain-to-source leakage currents. See Yuan Taur, “The Incredible Shrinking Transistor”, IEEE SPECTRUM, pages 25-29 (www.spectrum.ieee.org, ISSN 0018-9235, Jul. 1999).
FIG. 1
illustrates an exemplary long-channel conventional MOS device (
100
) that comprises an impurity doped source (
101
), an impurity doped drain (
102
), a conventional MOS type gate stack (
103
), and a laterally uniform channel doping profile (
104
) in the substrate to assist in the control of source-to-drain leakage currents. Devices are electrically isolated from each other via a field oxide (
105
). Such channel dopant profiles are common in devices with channel lengths down to approximately 200 nanometers (nm).
However, as device channel lengths have been reduced into the 100 nm regime the literature teaches that channel doping profiles that are non-uniform in both the lateral and vertical directions are required. Referencing
FIG. 2
, the exemplary short-channel MOS device (
200
) has some elements similar to the long-channel MOS device (
100
). The structure comprises a conventional impurity doped source (
201
) and drain (
202
) as well as a conventional MOS gate stack (
203
) (width<~100 nm, corresponding to the channel length L). The structure further comprises shallow, impurity doped extensions for the source (
208
) and drain (
209
) electrodes which are used in conjunction with drain (
206
) and source (
207
) pocket doping as well as conventional channel doping (
204
) to control source to drain leakage currents. Source and drain electrodes (
201
) and (
202
) and their respective extensions (
208
) and (
209
) (the combination of all four of which comprise the tailored source/drain doping profile) are all of the same doping polarity (either N-type or P-type) and are of the opposite polarity from the channel (
204
) and pocket doping elements (
206
) and (
207
). Again, a field oxide (
205
) electrically isolates devices from each other.
In his paper entitled “25 nm CMOS Design Considerations” (1998 IEDM Technical Digest, page 789), Yuan Taur states:
“. . . an optimized, vertically and laterally non-uniform doping profile, called the super-halo, is needed to control the short channel effect.”
A similar statement has been made in the IEEE Spectrum magazine:
“. . . in the 100 to 130 nm lithography generation, an optimally tailored profile that is both vertically and laterally non-uniform (Super-Halo) is need to control [short channel effects].” See Linda Geppert, “The 100-Million Transistor IC”, IEEE SPECTRUM, pages 23-24 (www.spectrum.ieee.org, ISSN 0018-9235, July 1999).
Furthermore, virtually all the prior art that discusses device design for channel lengths less than 200 nm states or implies that channel doping profiles that are highly non-uniform in both the lateral and vertical directions are required for adequate control of drain-to-source leakage currents. For example, Hargrove in his paper “High-Performance sub 0.08 um CMOS with Dual Gate Oxide and 9.7 ps Inverter Delay (1998 IEDM, page 627) states
“In order to achieve optimal device performance . . . strong halos coupled with shallow junctions are required.”
The prior art is virtually unanimous in its statement that laterally and vertically non-uniform doping profiles, in the form of laterally non-uniform channel dopants and shallow source/drain extensions, are required for adequate control of short channel effects.
Pocket/Halo Implants
Laterally non-uniform channel doping profiles are almost exclusively introduced after the gate electrode has been defined and is in place. With the gate serving as an implant mask, dopants of the same type as those already in the substrate are introduced into the channel regions adjacent to the gate electrode's edges via ion-implantation. As mentioned previously, these are often referred to as “pocket” or “halo” implants. See Yuan Taur, “The Incredible Shrinking Transistor”, IEEE SPECTRUM, page 28 (www.spectrum.ieee.org, ISSN 0018-9235, July 1999).
While effective at reinforcing the electros
Dorsey & Whitney LLP
Pert Evan
Spinnaker Semiconductor, Inc.
LandOfFree
Short-channel schottky-barrier MOSFET device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Short-channel schottky-barrier MOSFET device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Short-channel schottky-barrier MOSFET device and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3337647