FPGA and embedded circuitry initialization and processing

Details FPGA and embedded circuitry initialization and processing FPGA and embedded circuitry initialization and processing

2002-01-09

2004-08-24

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S047000, C716S030000

Reexamination Certificate

active

06781407

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The invention relates generally to field programmable gate arrays having embedded fixed logic circuitry; and, more particularly, it relates to the coordinated initialization and processing of the embedded fixed logic circuitry and the field programmable gate array.
BACKGROUND OF THE INVENTION
Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacturer, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, and programmable gate arrays (PGA).
Field programmable gate arrays (FPGA) have become very popular for telecommunication applications, Internet applications, switching applications, routing applications, and a variety of other end user applications.
FIG. 1
illustrates a generic schematic block diagram of a field programmable gate array (FPGA)
10
. The FPGA
10
includes programmable logic fabric
12
(containing programmable logic gates and programmable interconnects) and programmable input/output blocks
14
. The programmable input/output blocks
14
are fabricated on a substrate supporting the FPGA
10
and are coupled to the pins of the integrated circuit, allowing users to access the programmable logic fabric
12
. The programmable logic fabric
12
may be programmed to perform a wide variety of functions corresponding to particular end user applications. The programmable logic fabric
12
may be implemented in a variety of ways. For example, the programmable logic fabric
12
may be implemented in a symmetric array configuration, a row-based configuration, a column-based configuration, a sea-of-gates configuration, or a hierarchical programmable logic device configuration.
FIG. 2
illustrates the programmable logic fabric
12
implemented in accordance with a symmetrical array configuration. As shown, a plurality of logic blocks
16
is configured as an array of rows and columns. Each of the plurality of logic blocks
16
may be programmed by the end user to perform a specific logic function. More complex logic functions may be obtained by interconnecting individually programmed logic blocks using a plurality of programmable interconnections
18
. Accordingly, between each of the logic blocks of each row and each column are programmable interconnections
18
.
The programmable interconnections
18
provide the selective connectivity between the logic blocks of the array of logic blocks
16
as well as between the logic blocks and the programmable input/output blocks
14
. The programmable interconnections
18
may be implemented using any programmable element, including static RAM cell technology, fuse and/or anti-fuse cell technologies, EPROM transistor technology, and/or EEPROM transistor technology. If the FPGA utilizes static RAM programmable connections, the connections can be made using a variety of components, including pass transistors, transmission gates, and/or multiplexers that are controlled by the static RAM cells. If the FPGA utilizes anti-fuse interconnections, the interconnections typically reside in a high impedance state and can be reprogrammed into a low impedance, or fused, state to provide the selective connectivity. If the FPGA utilizes EPROM or EEPROM based interconnections, the interconnection cells may be reprogrammed, thus allowing the FPGA to be reconfigured.
FIG. 3
illustrates a schematic block diagram of the programmable logic fabric
12
being implemented as a row based configuration. In this configuration, the programmable logic fabric
12
includes a plurality of logic blocks
16
arranged in rows. Between each row of the logic blocks are programmable interconnections
18
. The interconnections may be implementing utilizing any programmable storage elements, including RAMs (static, dynamic and NVRAM), fuse and/or anti-fuse technologies, EPROM technology, and/or EEPROM technology.
FIG. 4
illustrates a schematic block diagram of the programmable logic fabric
12
being implemented as a column-based configuration. Logic blocks
16
and programmable interconnections
18
in
FIGS. 3 and 4
are substantially similar.
FIG. 5
illustrates the programmable logic fabric
12
being implemented as a hierarchical programmable logic device. In this implementation, the programmable logic fabric
12
includes programmable logic device blocks
22
and programmable interconnections
18
. As shown, four programmable logic block devices
22
are in the corners with an interconnection block
18
in the middle of the logic device blocks. In addition, the interconnections include lines coupling the programmable logic device blocks
22
to the interconnection block
18
.
As is known, field programmable gate arrays allow end users the flexibility of implementing custom integrated circuits while avoiding the initial cost, time delay and inherent risk of application specific integrated circuits (ASIC). While FPGAs have these advantages, there are some disadvantages. For instance, an FPGA programmed to perform a similar function as implemented in an ASIC can require more die area than the ASIC. Further, the performance of a design using a FPGA may in some cases be lower than that of a design implemented using an ASIC.
One way to mitigate these disadvantages is to embed into an FPGA certain commonly used complex functions as fixed logic circuit. Therefore, a need exists for a programmable gate array that includes embedded fixed logic circuits yet retains programmable components.
SUMMARY OF THE INVENTION
The present invention involves a system and method for initiating an integrated circuit. The integrated circuit includes configurable logic blocks arranged and interconnected to form a programmable logic fabric that surrounds, at least in part, an opening. The integrated circuit also includes a fixed logic circuit, inserted into the opening such that the fixed logic circuit is surrounded by a number of the configurable logic blocks. In addition, the integrated circuit includes configuration logic which handles the programming and initialization of the programmable logic fabric and fixed logic. The fixed logic circuit and the programmable logic fabric are powered on and the fixed logic circuit is held in a known state. An entirety of the programmable logic fabric is then configured while the fixed logic circuit is held in the known state. Subsequently, the configuration logic initiates startup of the fixed logic circuit. After both the fixed logic circuit and the programmable logic fabric are fully enabled, they work together cooperatively. In this embodiment, the fixed logic circuit operates as a slave with respect to the configuration logic that operates as a master during configuration and startup. In a modification to these operations, the programmable fabric is partially configured, the fixed logic circuit is started up, and then the fixed logic circuit completes the configuration of the programmable fabric.
In an alternate embodiment, the fixed logic circuit operates as a master with respect to the programmable logic fabric that operates as a slave during startup and initialization. However, for this master/slave relationship to exist, the fixed logic circuit must be accessible from the input/output lines of the integrated circuit. However, the fixed logic circuit is embedded within the programmable logic fabric. Thus, according to this alternative embodiment, the fixed logic circuit is accessible via dedicated communication lines. In this embodimen

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