Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
2000-08-22
2004-06-01
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S002000, C710S028000, C710S038000, C710S039000, C710S107000, C713S152000
Reexamination Certificate
active
06745258
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of RAID controllers and their interaction with host processors. In particular, the invention relates to RAID controllers and other intelligent host-bus adapters intended for insertion into systems having multiple host processors, where more than one host processor may run threads that are permitted to submit I/O commands to a RAID controller.
BACKGROUND OF THE INVENTION
Computing systems having more than one processor are well known in the art of computing. Among these computing systems are computing systems of the Symmetric Multiple Processor (SMP) type. SMP computing systems available from such vendors as Compaq include those having multiple Alpha, VAX, or Intel Pentium processors. SMP systems based on the SUN SPARC and other processors are known in the art. SMP systems are called symmetric because two or more of the processors in the system have similar or identical instruction sets and application program tasks may be distributed between these processors.
SMP computer systems are commercially available that run under the Microsoft Windows-NT, UNIX derivatives such as TRU-64 UNIX, and LINUX.
It is known that many SMP operating systems designate a particular processor to be a master processor, responsible for receiving interrupts from I/O devices and dispatching information obtained therefrom to the processor requiring information about the interrupt. This technique is often dictated by the design of the hardware, since I/O devices are often coupled to only one of the processors of an SMP system.
It is known to be desirable to queue results from intelligent peripherals because this permits the peripherals to perform following operations while waiting for a host to act upon results. This is advantageous since processing each result can take significant time.
In a RAID (Redundant Array of Independent Disks) controller as known in the art, there is a single reply queue even if the RAID controller is intended for insertion into an SMP system. The reply queue may be located in the RAID system, or may be positioned in memory of the host and written to through DMA (Direct Memory Access) operations by the RAID controller. PCI compliant busses are often used to interconnect RAID controllers to the processors and memory systems of an SMP system.
When each command to the RAID system executes the RAID system generates a reply associated with that command as known in the art. The generated reply includes command completion status for both read and write commands, and may, but need not, include data for read commands. The reply is thereupon stored in a reply queue of the RAID controller.
If the reply queue is located in host memory, the RAID controller arbitrates for access to the bus and sends the reply to memory of the master host processor. If the reply queue is located in RAID memory, the RAID controller will often signal the master host processor with an interrupt, the master host processor will then read the reply from the queue. Once received by the master host processor, that processor must determine the processor, and possibly the thread, affected by the reply. That reply must thereupon be dispatched to the affected processor.
It is known that in some operating systems, such as Windows NT, communication of a reply from one processor to another requires that the processors be synchronized through a synchronization wait. This synchronization wait can consume significant time.
It is desirable to minimize the processor time associated with synchronization wait operations. It is also desirable to balance the loading among the processors of an SMP system, such that the master processor not have excessive load.
SUMMARY OF THE INVENTION
A RAID controller is intended for attachment to a PCI bus, with which it may communicate with two or more processors of a multiple-processor computing system.
There are reply queues associated with the RAID controller associated with each host processor of the system. For example, a RAID controller in a system having two host processors will have two reply queues. There may be additional host processors, in which case there will be additional reply queues. Each reply queue is used for replies to commands received from an associated host processor. Each reply queue is located in memory of the associated host processor.
When a command is received by the RAID controller from a host processor, the command is placed in a command queue of the RAID controller. The identity of the host originating the command is logged and kept in association with the command in the command queue. Commands are prioritized, dispatched, and executed from the command queue as known in the art of RAID controllers.
When each command executes, the RAID system generates a reply associated with that command. The generated reply is thereupon transferred over the bus to memory associated with the processor that originated the command, and stored in the reply queue associated with that host processor.
In an alternative embodiment, a reply queue of the RAID system is associated with each thread performing I/O operations and running on a processor of the system.
The present invention is believed applicable to intelligent host bus adapters of other types as well as to RAID controllers.
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Bond Andrew
Cleve Robert Van
Pellegrino Greg John
Casiano Angel
Gaffin Jeffrey
Hewlett--Packard Development Company, L.P.
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