Column repair circuit in ferroelectric memory

Details Column repair circuit in ferroelectric memory Column repair circuit in ferroelectric memory

2002-09-09

2004-06-15

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700, C365S145000

Reexamination Certificate

active

06751137

ABSTRACT:

The present invention claims the benefit of the Korean Patent Application No. P2001-58279 filed in Korea on Sep. 20, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile ferroelectric memory, and more particularly, to a column repair circuit in a non-volatile ferroelectric memory having column redundancy.
2. Background of the Related Art
In general, a nonvolatile ferroelectric memory device such as a ferroelectric random access memory (FRAM), for example, has a data processing speed equivalent to that of dynamic random access memory (DRAM), and the nonvolatile ferroelectric memory device retains data during a power OFF state.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having high residual polarization characteristics. The residual polarization characteristics permit the retention of data when an applied electric field is removed.
FIG. 1
illustrates a characteristic curve of a hysteresis loop of a ferroelectric material according to the related art. In
FIG. 1
, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). The ‘d’ and ‘a’ states correspond to ‘1’ and ‘0’, respectively.
FIG. 2
illustrates a unit cell of a non-volatile ferroelectric memory according to the related art. In
FIG. 2
, the unit cell is provided with a bitline B/L formed along one direction, a wordline W/L formed perpendicular to the bitline, a plateline P/L formed spaced from the wordline along a direction identical to the wordline, a transistor T
1
having a gate connected to the wordline and a source connected to the bitline B/L, and a ferroelectric capacitor FC
1
having a first terminal connected to a drain of the transistor T
1
and a second terminal connected to the plateline P/L.
The data input/output operation of the related art non-volatile ferroelectric memory will be explained.
FIG. 3A
illustrates a timing diagram of a write mode operation of a ferroelectric memory according to the related art, and
FIG. 3B
illustrates a timing diagram of a read mode operation of the non-volatile ferroelectric memory.
During a writing mode, an external chip enable signal CSBpad transits from a ‘high’ level to a ‘low’ level and, at the same time, an external write enable signal WEBpad transits from a ‘high’ level to a ‘low’ level. When address decoding is started in the write mode, a pulse applied to the wordline transits from a ‘low’ level to a ‘high’ level to select a specific cell. Accordingly, the wordline is held at a ‘high’ level, the plateline has a ‘high’ level signal applied thereto for one period and a ‘low’ level signal applied thereto for another period in sequence. In order to write a logical value ‘1’ or ‘0’ to the selected cell, a ‘high’ or ‘low’ level signal synchronized to the write enable signal WEBpad is applied to the bitline. Moreover, if a ‘high’ level signal is applied to the bitline and a signal applied to the plateline is at a ‘low’ level in a period, then a signal applied to the wordline is at a ‘high’ level state, thereby a logical value ‘1’ is written to the ferroelectric capacitor. If a ‘low’ level signal is applied to the bitline, and a signal applied to the plateline is at a ‘high’ level, then a logical value ‘0’ is written to the ferroelectric capacitor.
The operation for reading the data stored in the cell by the foregoing write mode operation will be explained.
If the chip enable signal CSBpad is transited from a ‘high’ level to a ‘low’ level from outside of the cell, all bitlines are equalized to a ‘low’ level voltage by an equalizer signal before the wordline is selected. Then, after the bitlines are disabled, an address is decoded, and the decoded address transits the wordline from a ‘low’ level to a ‘high’ level, to select the cell. A ‘high’ level signal is applied to the plateline of the selected cell to break a data corresponding to a logical value ‘1’ stored in the ferroelectric memory. If a logical value ‘0’ is stored in the ferroelectric memory, then a data corresponding to the logical value ‘0’ is not broken. The data not broken, and the data broken thus provide values different from each other according to the aforementioned hysteresis loop, so that the sense amplifier senses a logical value ‘1’ or ‘0’. That is, when the data broken is a case when the value is changed from ‘d’ to ‘f’ in the hysteresis loop in
FIG. 1
, and the case of the data not broken is a case when the value is changed from ‘a’ to ‘f’ in the hysteresis loop in FIG.
1
. Therefore, if the sense amplifier is enabled after a certain time period is passed, in the case of the data broken, a logical value ‘1’ is provided as amplified, and in the case of the data not broken, a logical value ‘0’ is provided as amplified. After the sense amplifier amplifies and provides the data, since an original data should be restored, the plateline is disabled from a ‘high’ level to a ‘low’ level during a state in which a ‘high’ level signal is applied to the wordline.
FIG. 4
illustrates a block diagram of a non-volatile ferroelectric memory according to the related art. In
FIG. 4
, the non-volatile ferroelectric memory is provided with a main cell array part
41
having a lower part allocated for a reference cell array part
42
, a wordline driver part
43
on one side of the main cell array part
41
for applying a driving signal to the main cell array part
41
and the reference cell array part
42
, and a sense amplifier part
44
under the main cell array part
41
. The wordline driver part
43
provides a driving signal to a main wordline in the main cell array part
41
, and a reference wordline in the reference cell array part
42
. The sense amplifier part
44
has a plurality of sense amplifiers each for amplifying a signal received from the bitline or the bitbarline.
The operation of the non-volatile ferroelectric memory will be explained, with reference to FIG.
5
.
FIG. 5
illustrates a detail of
FIG. 4
, wherein the main cell array has a folded bitline structure like a DRAM. In
FIG. 5
, the reference cell array part
42
has a folded bitline structure, and a reference cell wordline and a reference cell plateline formed in a pair. The reference cell wordline and the reference cell plateline pairs are defined as RWL_
1
/RPL_
1
, and RWL_
2
/RPL_
2
. When a main cell wordline MWL_N−1 and a main cell plateline MPL_N−1 are enabled, the reference cell wordline RWL_
1
and the reference cell plateline RPL_
1
are enabled, to load a main cell data on the bitline, and a reference cell data on the bitbarline BB/L. When a main cell wordline MWL_N and a main cell plateline MPL_N are enabled, the reference cell wordline RWL_
2
and the reference cell plateline RPL_
2
are enabled, to load a main cell data on the bitbarline BB/L, and a reference cell data on the bitline B/L. A bitline voltage REF from the reference cell is between B H (High) and B L (Low), both are bitline voltages from the main cell. Therefore, in order to have the reference voltage REF to be between B_H and B_L, the reference cell may be operated by either of two methods.
A first method is storing a logical “1” in a capacitor in the reference cell by forming a size of the reference cell capacitor to be smaller than a size of a main cell capacitor. A second method is storing a logical “0” in a capacitor in the reference cell by forming a size of the reference cell capacitor to be greater than a size of a main cell capacitor. Thus, the non-volatile ferroelectric memory provides the reference voltage the sense amplifier requires 44 by using the two methods.
FIG. 6
illustrates a sense amplifier according to the related art included in the sense amplifier part in FIG.
4
. In
FIG. 6
, the sense amplifier is an inverter of a latch type, inclusive of two PMOS transistors, and two NMOS tran

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