Method and circuit for enabling a clock-synchronized...

Details Method and circuit for enabling a clock-synchronized... Method and circuit for enabling a clock-synchronized...

1999-09-13

2004-06-01

Peikari, B. James (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S169000, C712S212000, C710S020000, C710S045000

Reexamination Certificate

active

06745302

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device capable of performing a high speed read modify write (hereinafter referred to as an “RMW”) operation aimed at a z- buffer for performing hidden-surface processing in the field for example of three dimensional computer graphics (hereinafter referred to as “3DCG”).
2. Description of the Related Art
In recent years, high speed, large capacity memories, for example, a clock synchronization (synchronous) dynamic random access memories (DRAM) and a run-bus specification type have appeared.
Further, the field of 3DCG is rapidly spreading due to the improvement of the performances of personal computers, family computer game machines, etc. on the one hand and demands for higher speed and larger capacity memory than the past as the image memory for 3DCG.
For one application of an image memory, there are a frame buffer for storing drawing data and a z- buffer for storing a z- coordinate necessary for performing the hidden-surface processing indispensable for 3DCG.
In hidden-surface processing, polygonal drawing information referred to as polygons is generated. The size of the z- coordinate is compared with the periphery to calculate whether the polygon exists before or after other polygons, and processing of a drawing image is carried out by the polygons existing before the other polygon.
Accordingly, in the z- buffer for storing the z- coordinate, it is necessary to read the z- address of each polygon and perform the write modification after comparison with the other z- address. The operation thereof is basically an RMW operation.
FIG. 1
is a block diagram of a related art clock synchronization type memory.
In the figure, reference numeral
20
denotes a memory array,
22
an address decoder,
24
a register for temporarily holding an input signal of the address decoder
22
,
26
an input buffer, and
28
an output buffer. Further, ADD represents an address signal, R/W-Data represents input/output data, and OE-cnt. represents an output control signal.
At present, in a generally commercially available general purpose memory, the same terminals are used for input/output of the data to and from the memory array
20
for decreasing the number of pins of the package as shown in
FIG. 1
, and the input and output of the data is switched by an output control signal OE-cnt. Namely, the input buffer
26
and the output buffer
28
are connected in parallel in inverse directions. The output buffer
28
is not operated when there is no input of the output control signal OE-cnt.
FIG. 2
is a flowchart of the operation when making general purpose memory perform an RMW operation for performing the hidden-surface processing of 3DCG.
In the figure, symbols A
0
, A
1
, denote address numbers in the memory array. The address signal ADD in the command is decoded (Ad-Dec) for every clock signal CLK with respect to the memory cell of this address number and output (D-out) after the stored data is read out (mem-R). After this data output, the z- address is subjected to the comparison processing in the next several clock sections, and the write modification to an original address in the memory is carried out. This RMW operation is continuously repeated in units of several addresses while shifting each address by one pulse each by the clock signal CLK.
In actuality, about three clocks are enough for the comparison processing per se, but in this illustrated example, continuous processing is carried out in units of six addresses. Further, as described above, it is necessary to use the same terminals for input/output, shift the output buffer
28
to the non-operating state by the output control signal OE-cot. at the switching thereof, and guarantee a high input impedance, therefore eight clock sections are required until the write modification from the data output is carried out in each address. For this reason, when viewing this from the command, as illustrated, a waiting section (in this case,
4
clocks worth) becomes necessary in the period of from R
5
to W
0
, and the efficiency of RMW is bad.
In order to shorten the waiting section of this command, it can be considered too to make the address unit to be continuously processed small and shorten the clock section until the write modification from the data output of each address is carried out, but the number of times of switching of the output buffer
28
will be increased by this. For this reason, there is a limit in also the shortening of the command waiting section, and the control becomes complex if the input/output terminal is frequently switched.
In order to avoid this command waiting time, as shown in
FIG. 3
, the commonly used input/output pin can be separated.
When this separated input/output type memory is used for the RMW operation, as shown in the timing chart of
FIG. 4
, the waiting section of a command can be eliminated.
In a memory having the configuration shown in
FIG. 3
, it suffers from the disadvantage that the number of pins is increased, thus it was not practical, but a great increase of the bit width has become possible by the memory/logic mixing process in recent years, therefore the efficiency of the RMW can be enhanced to a certain extent by using this type of memory.
However, even if this method is adopted, as shown in
FIG. 4
, the input of the address signal is made common at the time of reading and writing of the data so as to suppress an increase in the number of pins, therefore the read/write operation of data still takes two clock sections and, thus, in this meaning, it does not lead to a drastic enhancement of efficiency of a RMW.
Namely, when it is desired to further improve the drawing performance of 3DCG, the fact that a plurality of clock sections are required for every read/write operation of the data becomes a major obstacle.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device which makes it possible to perform the data write and read operations in the same clock section for a memory operating in clock synchronization and capable of continuously performing a high speed RMW operation.
According to a first aspect of the present invention, there is provided a semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written and read; a read address decoding means for independently decoding a read address of a memory cell in response to a first designated address; a write address decoding means for independently decoding a write address of a memory cell in response to a second designated address; a data reading means for reading data of a memory cell addressed by said decoded read address in said read address decoding means; and a data writing means for writing data to a memory cell addressed by the decoded write address in the write address decoding means.
According to a second aspect of the present invention, there is provided a semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read; a read address decoding means for independently decoding an address of a read memory cell in response to a first designated address; a write address decoding means for independently decoding a write address of a memory cell in response to a second designated address; a data reading means for reading data of a memory cell addressed by the decoded read address in the read address decoding means; a data writing means for writing data to a memory cell addressed by the decoded write address in the write address decoding means; and an address delay means by which the decoded write address decoded by the write address decoding means is delayed by a predetermined time from a read address decoded by the read address decoding means, the predetermined time being set as a predetermined plurality of times of basic synchronization

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