Loop error detector for use in a PN code timing tracking loop

Details Loop error detector for use in a PN code timing tracking loop Loop error detector for use in a PN code timing tracking loop

2001-09-26

2004-06-15

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

C375S130000, C375S137000

Reexamination Certificate

active

06751278

ABSTRACT:

PRIORITY
This application claims priority to an application entitled “Loop Error Detector for Use in a PN Code Timing Tracking Loop” filed in the Korean Industrial Property Office on Sep. 27, 2000 and assigned Serial No. 2000-56739, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to Code Division Multiple Access (CDMA) radio communication, and in particular, to a loop error detector for use in a Pseudo Noise (PN) code timing tracking loop.
2. Description of the Related Art
In a CDMA communication system, mobile stations must initially restore the timing of signals transmitted from a base station in order to receive the transmitted signals. To accomplish this, the CDMA communication system performs a timing acquisition and tracking using a PN code sequence. After a coarse timing acquisition of, for example, 1 or a ½ chip is performed through a code search operation, a fine timing tracking operation of, for example, ⅛ chip is initiated. This fine timing tracking operation is typically performed using a code tracking loop with a secondary loop filter.
A conventional code tracking loop typically employs a Tau-Dither Tracking Loop (TDL) structure with a secondary loop filter rather than a Double Dither Tracking Loop (DDL) structure. The reason for not using the DDL structure in spite of its good noise characteristics and even performance in terms of other characteristics, is because it increases the hardware size and although it satisfies the required performance of the conventional radio communication system, which services only the voice, it does so at a relatively lower moving speed. In order to provide a high-speed data service at the higher moving speed of the user as in an IMT-2000 system, a timing tracker is required which is stable against noises and has an improved performance. To this end, many attempts have been made to utilize the DDL structure and a third loop filter.
The conventionally employed TDL tracking loop structure is illustrated in FIG.
1
. Referring to
FIG. 1
, a correlation between a received signal s(t) and an early PN code PN_R or a late PN code PN_L generated by a PN code generator
18
, the PN codes PN_R and PN_L having a ½-chip phase difference, is calculated by a selector
20
, a multiplier
10
, and accumulators
22
and
24
in a loop error detector
12
. The early PN code PN_R and the late PN code PN_L are expressed by Equations (1) and (2), respectively, and the received signal is expressed by s(t)=S
I
(t)+jS
Q
(t). In the following equations, T
d
indicates chip time.
C
⁡
(
t
+
T
d
2
)
=
C
1
·
(
t
+
T
d
2
)
+
j
⁢
 
⁢
C
Q
·
(
t
+
T
d
2
)
(
1
)
C
⁡
(
t
-
T
d
2
)
=
C
1
·
(
t
-
T
d
2
)
+
j
⁢
 
⁢
C
Q
·
(
t
-
T
d
2
)
(
2
)
The selector
20
selects the early PN code PN_R and the late PN code PN_L according to a q(t) signal and provides the selected PN code to the multiplier
10
. The selecting period includes N chips and is determined in association with a symbol period at the lowest data rate used and a Walsh code period for channel separation. The q(t) signal applied to the selector
20
is toggled between ‘1’ and ‘−1’ at a period of N chips. The PN code calculated in this method is complex-multiplied by the received signal by the multiplier
10
, to despread the received signal. An in-phase signal or I-channel signal R
I
(t) and a quadrature-phase signal or Q-channel signal R
Q
(t) of an output signal, R(t)=R
I
(t)+jR
Q
(t), of the multiplier
10
are correlated for an N-chip period by the accumulators
22
and
24
, respectively, as expressed by Equations (3-1) and (3-2) below. In the following equations, “N” is the chip period of a PN sequence and “k” is N−1.
I
⁡
(
t
)
=
1
k
·
∑
n
=
0
N
⁢
R
I
⁡
(
n
)
(3-1)
Q
⁡
(
t
)
=
1
k
·
∑
n
=
0
N
⁢
R
Q
⁡
(
n
)
(3-2)
To calculate signal power, squarers
26
and
28
square I(t) and Q(t), respectively, and then, an adder
30
adds the squared values. An output signal A(t) of the adder
30
is updated at the period of N chips, and a subtracter
32
calculates a difference between the power of the late phase signal and the power of the early phase signal by calculating a difference between the present value A(t) and a previous value A(t−1) determined for the previous N-chip period. Thereafter, the calculated power difference is multiplied by a −q(t) signal by a multiplier
34
and is output as a loop error signal e(t).
The calculated loop error signal e(t) is corrected, through a secondary loop filter
14
and a voltage controlled oscillator (VCO)
16
, by a reference timing error value for the loop error value of the loop error signal e(t). The PN code generator
18
generates a PN code at every chip in response to the error-corrected timing signal. Such a PN code generator
18
is comprised of an N-stage Left Feedback Shift Register (LSFR).
The accumulators
22
and
24
, the squarers
26
and
28
, the adder
30
, the subtracter
32
and the multiplier
34
constitute the loop error detector
12
for detecting a TDL phase error. Such a loop error detector, as illustrated in
FIG. 2
, can also be comprised of accumulators
36
and
38
, a multiplexer
40
, a squarer
42
, an adder
44
, a subtracter
46
and a multiplier
48
.
Unlike the loop error detector of
FIG. 1
which calculates I(t)
2
and Q(t)
2
for N chips using the two squarers
26
and
28
, the loop error detector of
FIG. 2
first calculates I(t)
2
using a multiplexer
40
for alternately selecting I(t) and Q(t), and one squarer
42
, and then calculates Q(t)
2
; or first calculates Q(t)
2
and then calculates I(t)
2
. By doing so, the loop error detector of
FIG. 2
decreases the number of the squarers to one. The succeeding procedure, in which the sequentially calculated I(t)
2
and Q(t)
2
are added by the adder
44
and the loop error signal e(t) is calculated by the subtracter
46
and the multiplier
48
, is equivalent to the procedure described in FIG.
1
.
A conventional DDL tracker is illustrated in
FIG. 3
, in which the secondary loop
14
, the VCO
16
and the PN code generator
18
are identical to those in
FIG. 1
but a loop error detector
54
is different from the TDL loop error detector
12
of FIG.
1
. While the TDL loop error detector
12
calculates the early phase signal level and the late phase signal level with a predetermined time lag, the DDL loop error detector
54
simultaneously measures the two signal levels at the same time point. The DDL tracker of
FIG. 3
has double the hardware structure, since it includes multipliers
50
and
52
, accumulators
56
-
62
, squarers
64
-
70
, and adders
72
and
74
, while the TDL tracker of
FIG. 1
includes only the multiplier
10
, the accumulators
22
and
24
, the squarers
26
and
28
, and the adder
30
. In
FIG. 3
, the multipliers
50
and
52
perform complex multiplication for dispreading an input signal s(t) as in the multiplier
10
of FIG.
1
. The complex multiplication is simultaneously performed on both the early PN code PN_R and the late PN code PN_L. The input signal s(t) is applied equally to the early PN code PN_R and the late PN code PN_L, contributing to the improvement of a balance property between the early signal and the late signal. The respective phase signals R
1
(
t
) and R
2
(
t
) are accumulated by the accumulators
56
-
62
for N chips to calculate correlations, squared by the squarers
64
-
70
, and then, added by the adders
72
and
74
. As a result, the adder
72
determines a level of an early signal A
1
(
t
) and the adder
74
determines a level of a late signal A
2
(
t
). A level difference between the determined signals A
1
(
t
) and A
2
(
t
) is calculated by a subtracter
76
, and the determined level difference becomes a loop error signal e(t). It is noted from the foregoing description that the DDL loop error detector
54
of
FIG. 3
has twi

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