High speed current mode logic gate circuit architecture

Details High speed current mode logic gate circuit architecture High speed current mode logic gate circuit architecture

2002-08-27

2004-06-15

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

C326S126000, C326S115000, C326S104000

Reexamination Certificate

active

06750681

ABSTRACT:

FIELD OF THE INVENTION
The invention is in the domain of source-coupled logic implemented in large scale integrated (LSI) radio frequency technology.
BACKGROUND OF THE INVENTION
Metal Oxide Silicon (MOS) Current Mode Logic (CML), (sometimes known as Common Mode Logic), has several interesting properties that make it desirable for low power and high performance designs. First, the circuits operate with a small voltage swing, typically in the order of 0.2 to 0.4 Volts. This decreased voltage swing permits much faster switching although it may decrease the robustness of the circuit with respect to noise margins. CML gates also draw a relatively constant amount of current from the power supply, a property that significantly reduces the amount of noise (in the form of spikes) on the supply and substrate voltages. This reduction in noise is extremely desirable in mixed signal environments where the analog circuitry is especially susceptible to switching noise from the digital logic. Another beneficial property of CML circuits is that they are differential in nature, which provides good noise immunity to common-mode signals such as supply bounce.
In existing integrated circuits designed using Current Mode Logic (CML) technology, the problem of adjusting the output voltage levels of preceding gates to the voltage input levels expected in the succeeding gates is well-known. In many designs the approach taken is to introduce level-shifting (active) devices (transistor buffers) which achieve the objective of adjusting the level, but do so at the cost of extra power consumption and increased propagation delay. The overall effect is to reduce the maximum operating frequency achievable for a given design and technology. Other approaches include the use of passive level shifters, that is a network of resistors and capacitors, which have similar shortcomings. A further solution sometimes seen is to alternate the logic (negative/positive) so that the logic input levels of stages following may be chosen to match the output levels of the preceding stage, and the circuit adapted to produce the desired logical effect. However, the logic levels are not consistent across the whole circuit or system, and this solution can cause some confusion during design, since the logic input levels required for a given stage and the logic itself needs to be designed carefully, in some cases requiring a further stage of logic. Any extra stages of logic result in increased propagation delays.
By way of an example, in prior art implementations, the input levels and output levels may be implied from the exemplary circuit as shown in
FIG. 1
, which shows a complementary two-input AND gate, symbolically
180
, and schematically,
190
. A similar immediately succeeding stage or gate using this design could not have complementary inputs such as A and {overscore (A)} being fed from the complementary outputs C and {overscore (C)} without some form of intermediate stage to adjust the logic levels, unless special design steps or precautions were taken as previously discussed. Further, it can be seen that it is difficult to design the voltages of the high logic level and low logic level independently since they make use of the shared load resistors
150
,
160
and are served by a common current source
140
.
SUMMARY OF THE INVENTION
The invention described herein overcomes some or all of the previously mentioned shortcomings and other problems in circuits using traditional CML technology, removing the need for level conversions between successive logic stages. This is achieved by matching the output levels and succeeding input levels, using a unique technique, or gate architecture, we call Enhanced Pseudo Current Mode Logic (EPCML). The invention permits the implementation of AND, OR and XOR gates, and their corresponding (negating) equivalents NAND, NOR, NXOR. As is well known in the art, almost all more complex functions can all be constructed using various combinations of these gates.
The new EPCML gate architecture described herein can be applied to Complementary MOS (CMOS), Bipolar/CMOS (BiCMOS), and other analog or mixed analog/digital technologies today and is adaptable to future technologies as well. As mentioned earlier, this gate architecture retains the advantages of conventional circuits of this type, at the same time eliminating several of the problems associated with them, including:
1. Suitable for low voltage operation.
2. Operates in a pseudo-differential manner.
3. Provides adequate noise margins.
4. Removes the need for level conversion between logic gates, so that overall circuit speed is faster than the equivalent CML implementation.
The invention described herein therefore allows extra degrees of freedom in the design of CML gates, permitting easier matching of the logic levels of outputs and succeeding inputs, and in consequence allowing circuits to be designed and implemented which offer higher operating frequencies using the same technology when compared to those designed and implemented using other techniques.
Put simply, the invention comprises splitting the complementary logical circuit completely in half and connecting the inputs of each half (half-gate) to appropriate complementary signals. The designer is therefore able to adjust the levels of the complementary output signals independently and thereby match them to the input levels required for the immediately succeeding complementary stage. While the total number of components in the gate has increased significantly, no extra components are required to match the output of the logic stage to the input of the next (succeeding) logic stage, thereby at least partly mitigating the effects of the extra circuitry on the overall size of the circuit. Prior art implementations would require the interposing of a level conversion stage, using either active or passive components or combinations thereof. The removal of the need for the interposing stages results in an overall faster response, since, as would be understood by one skilled in the art, such extra stages must delay the signal (because of the need to propagate the signal through these extra components). These extra stages also add distortion to the signal. Thus Enhanced Pseudo Current Mode Logic (EPCML) is a practical and elegant solution that provides for circuits operating at higher frequencies than was practical previously. In short, the invention simulates the effect of traditional CML, but overcomes at least some of its disadvantages.
Although some degree of interference rejection is sacrificed in implementing this invention, this loss of interference rejection is considered a reasonable compromise in those situations where the logic is highly integrated, the gates are implemented with closely matched half-gates, and transmission paths are short and matched. At other points in a particular circuit such a compromise may not be acceptable and the designer may need to use different techniques to reduce the overall propagation times if required. Careful and intelligent design can ensure that such decisions are made consistent with optimising the overall design. For example, if the designer restricts all of the high speed components to the fully integrated environment, and only allows lower speed signals to leave that environment, propagation delays and any interfering noise will have relatively little effect.
Further, the designer must decide whether the extra size of the circuit as implemented with the invention is more important than the ability to achieve the enhanced high frequency performance.
In summary, the output high logic voltage and the output low logic voltages are established to match the input high logic voltage and the input low logic voltage respectively of a succeeding integrated logic gate subsystem. This is achieved separately for each of two symmetric complementary balanced circuits, by:
selecting a bias current value;
selecting a bias resistor value to set the output high logic voltage so that it is within the acceptance range of the succeeding input high logic voltage; an

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