Strained channel finfet

Details Strained channel finfet Strained channel finfet

2003-01-23

2004-10-12

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S192000

Reexamination Certificate

active

06803631

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to transistors and, more particularly, to fin field effect transistors (FinFETs).
BACKGROUND ART
Scaling of device dimensions has been a primary factor driving improvements in integrated circuit performance and reduction in integrated circuit cost. Due to limitations associated with existing gate-oxide thicknesses and source/drain (S/D) junction depths, scaling of existing bulk MOSFET devices below the 0.1 &mgr;m process generation may be difficult, if not impossible. New device structures and new materials, thus, are likely to be needed to improve FET performance.
Double-gate MOSFETs represent new devices that are candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, the use of two gates to control the channel significantly suppresses short-channel effects. A FinFET is a recent double-gate structure that includes a channel formed in a vertical fin. The FinFET is similar to existing planar MOSFET in layout and fabrication. The FinFET also provides a range of channel lengths, CMOS compatibility and large packing density compared to other double-gate structures.
DISCLOSURE OF THE INVENTION
Consistent with the present invention, a FinFET transistor is provided that uses a vertically formed strained channel layer that is self-aligned to the fin channel. The strained channel layer may include a crystalline material that is lattice constant mismatched with the crystalline material of the fin of the FinFET. The lattice constant mismatch induces tensile strain within the strained channel layer that increases carrier mobility. Increasing the carrier mobility, in turn, increases the drive current of the FinFET transistor, thus, improving FinFET performance.
Additional advantages and other features of the invention will be set forth in part in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following, or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor structure that includes a fin. The fin includes a first crystalline material and a plurality of surfaces. The structure further includes a layer formed on at least a portion of the plurality of surfaces, the layer including a second crystalline material. The first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the layer.
According to another aspect of the invention, a transistor is provided. The transistor includes a fin that further includes a first crystalline material and first and second end portions. The first crystalline material has a first lattice constant. The transistor further includes source and drain regions formed adjacent the first and second end portions of the fin. The transistor also includes a first layer of second crystalline material formed on at least a portion of the fin. The second crystalline material has a second lattice constant, wherein the first lattice constant is greater than the second lattice constant. The transistor additionally includes a dielectric layer formed on at least a portion of the first layer and a gate electrode formed on at least a portion of the dielectric layer.
According to a further aspect of the invention, a method of forming a semiconductor device is provided. The method includes forming a fin that includes a first crystalline material and multiple surfaces. The method further includes forming a first layer on at least a portion of the multiple surfaces. The first layer includes a second crystalline material, wherein the first crystalline material is lattice constant mismatched with the second crystalline material to induce tensile strain within the first layer.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 6475869 (2002-11-01), Yu
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6635909 (2003-10-01), Clark et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub 50-nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.

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