Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2000-09-28
2004-11-30
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S322000
Reexamination Certificate
active
06826702
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to power consumption reducing methods for various radio telephone sets such as portable/car telephone sets (or cellular sets) and personal handyphone systems having cordless telephone function and cellular function and various radio sets such as pocket bells, personal radio sets and civil radio sets (CB) and also to radio sets and, more particularly, to power consumption reducing systems or radio sets, in which it is possible to reduce power consumption of a central processing unit (CPU) for controlling various components therein and also to radio sets adopting the same methods.
Japanese Patent Laid-Open No. 10-161780 discloses a power consumption reducing method in a conventional portable terminal. The disclosed portable terminal comprises a CPU, a clock oscillator, a key input detector and an interruption controller with a time division multiplex system. When the portable terminal is set in an intermittent receiving mode, the CPU feeds out a suspension signal to the clock oscillator to suspend the oscillation of the clock oscillator and set up a suspension mode. Subsequently, when the key input detector detects the operation of the keyboard, it feeds out a signal to an interruption controller. At this time, the interruption controller starts the clock oscillator. When the oscillation is stabilized, the clock oscillator supplies a clock signal to the CPU. After the oscillation of the clock oscillator has been stabilized, the interruption controller switches the mode of the CPU. With this construction, it is possible to reduce the operation currents in the CPU and the clock oscillator.
Japanese Patent Laid-Open No. 11-88254 discloses a power consumption reducing method for a conventional radio set. A CPU in this example of radio set controls an operation for the CPU by controlling an operation clock feed-out element with software according to its processing load. With this construction, it is possible to optimize the power consumption of the CPU.
However, the power consumption reducing method for the conventional portable terminal disclosed in the Japanese Patent Laid-Open No. 10-161780 adopts the time division reducing method for communication, and is applicable to only radio sets, which can be set in the intermittent receiving mode. In other words, the disclosed method has a drawback that it can not be applied to radio sets adopting systems other than the time division multiplex system for communication or to radio units, which transmit and receive data continuously without being set in any intermittent receiving mode and also adopts the time division multiplex system is adopted for communication. That is, the method is poor in versatility.
In the power consumption reducing method for the conventional radio unit disclosed in the Japanese Patent Laid-Open No. 11-88254, the CPU itself has to measure its own processing load and control the operation clock feed-out element. Therefore, software for the power consumptiom reducing process is required separately in addition to that for the normal processing. Besides, the CPU should bear extra burden for the power consumption reducing process, and the power consumption is rather increased. It is thus impossible to efficiently reduce the power consumption.
SUMMARY OF THE INVENTION
The present invention was made in the light of the above background, and it has an object of providing a power consumption reducing method for a radio set, which features rich versatility, require no special software, is free from any extra burden on the CPU and permits efficiently reducing the power consumption.
According to an aspect of the present invention, there is provided a power consumption reducing method for a radio set, wherein: a frequency of a clock signal fed out to a central processing unit for controlling various parts of the radio set is controlled on the basis of proportional-to-load signal, which is fed out from the central processing unit and substantially in a proportional relation to the variation of the load on the central processing unit.
According to another aspect of the present invention, there is provided a power consumption reducing method for a radio set, wherein: a frequency of a clock signal fed out to a central processing unit for controlling various parts of the radio set is controlled on the basis of the number of pulses of the proportional-to-load signal fed out from the central processing unit in a predetermined period of time.
According to other aspect of the present invention, there is provided a power consumption reducing method for a radio set, wherein: a frequency of a clock signal fed out to a central processing unit for controlling various parts of the radio set is controlled on the basis of the number of pulses of the proportional-to-load signal fed out from the central processing unit in a predetermined period of time so that the frequency of the clock signal is increased when the number of pulses of the proportional-to-load signal is greater than a predetermined threshold value, is reduced when the number of pulses is less than the threshold value, and is held without being changed when the number of pulses is the same as the threshold value.
According to still other aspect of the present invention, there is provided a power consumption reducing method for a radio set, wherein: a frequency of a clock signal fed out to a central processing unit for controlling various parts of the radio set is controlled on the basis of the number of pulses of the proportional-to-load signal fed out from the central processing unit in a predetermined period of time so that the frequency of the clock signal is increased when the number of pulses of the proportional-to-load signal is greater than a predetermined threshold value, is reduced when the number of pulses is less than the threshold value, and is held without being changed when the number of pulses is the same as the threshold value, and the threshold value is increased by a predetermined value when the number of pulses is greater than the threshold value, is reduced by a predetermined value when the number of pulses is less than the thresholds value, and is held without being changed when the number of pulses is the same as the threshold value.
The proportional-to-load signal is a read signal instructing the reading of data or a write signal instructing the writing of data.
According to further aspect of the present invention, there is provided a radio unit comprising: a central processing unit for controlling various parts of the radio set to realize a radio communication function; an oscillator for generating a clock signal at frequency controlled on the basis of a control signal and feeding out the clock signal to the central processing unit; and a frequency control circuit for generating the control signal on the basis of a proportional-to-load signal, which is fed out from the central processing unit and substantially in a proportional relation to the variation of the load on the central processing unit.
According to still further aspect of the present invention, there is provided a radio unit comprising: a central processing unit for controlling various parts of the radio set to realize a radio communication function; an oscillator for generating a clock signal at frequency controlled on the basis of a control signal and feeding out the clock signal to the central processing unit; and a frequency control circuit for generating the control signal on the basis of the number of pulses of a proportional-to-load signal which is fed out from the central processing unit in a predetermined period of time and substantially in a proportional relation to the variation of the load on the central processing-unit.
The frequency control circuit includes a timing signal generator, a counter, a threshold register, a comparator and a control signal generator; the timing signal generator generates a first timing signal becoming active for every predetermined cycle period according to the clock signal, and a second to a fourth
NEC Corporation
Perveen Rehana
Sughrue & Mion, PLLC
Yanchus, III Paul
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