Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-06-19
2004-02-10
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S028000, C714S039000
Reexamination Certificate
active
06691258
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus control unit for star architectures having trace support and/or for supporting program flow monitoring, to a program flow monitoring system using this bus control unit and to a method for program flow monitoring.
2. Description of the Prior Art
To monitor and test software programs, it is necessary, in many applications, to monitor the program in its actual hardware environment in order to find dynamic software errors which only become apparent in A “use”. In particular, in switching systems for telecommunications which have extremely complex software, such a possible way of performing “debugging” of the software is necessary and extremely useful.
FIG. 1
shows a block diagram of a processor architecture according to the prior art. In
FIG. 1
, the reference symbol
1
designates a central processor unit or CPU, and the reference symbol
2
designates a coprocessor, or an additional central processing unit, which supports the central processing unit
1
.
3
designates an input/output unit,
5
designates a common main storage and
6
designates a program flow monitoring device or tracer. The central processing unit
1
, the coprocessor
2
, the input/output unit
3
, the main storage
5
and the program flow monitoring device
6
are connected to one another via a common bus
4
.
Software programs which use the processor architecture with a common bus according to
FIG. 1
are usually initially checked and tested with respect to their functional capability by software. However, when the program is used in the actual hardware environment according to
FIG. 1
, further software errors can occur owing to the multiplicity of external parameters, and searching for these software errors is extremely time-consuming and difficult. In order to simplify this “debugging” of the software or of the error search in the software program, the tracer or program flow monitoring device
6
is connected to the common bus
4
in a hardware environment which is actually used, such as that illustrated, in FIG.
1
. This tracer
6
records the entirety of the data stream which is present at the common bus
4
and which flows between the central processing unit
1
, the coprocessor
2
, the input/output unit
3
and the main storage
5
. As a result, software errors which occur in actual use can be found and eliminated relatively easily.
However, the processor architecture with a common bus according to
FIG. 1
has the disadvantage that the data transmission rates on the common bus
4
are relatively low because the bus has a comparatively low bus frequency and the bus-seizure times are long.
Therefore, by way of replacement, a star architecture has been designed in which the respective data processing units are arranged in a star-shaped configuration and do not have a common bus. Because the individual buses in the star-shaped topology can be operated at higher frequencies and their seizure times are independent of one another, higher data rates are thus obtained.
FIG. 2
shows a block diagram of a processor architecture with a star topology according to the prior art. In
FIG. 2
, the reference symbol
1
again designates the central processing unit CPU, the reference symbol
2
designates the coprocessor, the reference symbol
3
designates the input/output unit and the reference symbol
5
designates the common main storage. The respective data processing units
1
,
2
,
3
and
5
are connected to one another in a star-shaped configuration via a bus control unit
7
. Here, the central processing unit
1
is connected to the bus control unit
7
via a processor bus
8
, while the coprocessor
2
is connected to the bus control unit
7
via a coprocessor bus
11
. In the same way, an input/output bus
9
connects the bus control unit
7
to the input/output unit
3
, and a storage bus
10
connects the bus control unit
7
to the common main storage
5
. As illustrated in
FIG. 2
, the star-shaped topology has the advantage over the processor architecture with common bus according to
FIG. 1
in that, for example, a data stream I can flow between the coprocessor
2
and the input/output unit
3
via the bus control unit
7
and the coprocessor bus
11
and the input/output bus
9
, while a data stream II flows from the central processing unit
1
to the common main storage
5
via the processor bus
8
, the bus control unit
7
and the storage bus
10
. In the same way, a data stream III can flow between the central processing unit
1
and the coprocessor
2
, independently of a data stream IV from the input/output unit
3
to the main storage
5
.
However, these advantages of a processor architecture with star topology according to the prior art have a significant disadvantage with respect to the debugging or monitoring possibilities via the tracer
6
.
Because there is no common bus
4
in the star topology of
FIG. 2
, the tracer or program flow monitoring unit
6
does not have a common interface at which all the data of the system can be monitored. Consequently, to debug a software program, each data processing unit must be observed independently and separately from the others. In order to observe the data stream I, it is necessary according to
FIG. 2
to connect the tracer
6
to the input/output bus
9
, for example. To observe the data stream II between the central processing unit
1
and the main storage
5
, the tracer
6
must be connected to the storage bus
10
. As an alternative, the tracer
6
also could be connected to the coprocessor
11
in order to observe the data stream I flowing between the coprocessor and input/output unit. To monitor the data stream II, it is also possible to connect the tracer
6
to the processor bus
8
.
Simple and cost-effective troubleshooting therefors is not possible with a conventional processor architecture with star topology.
The invention is thus directed to providing a bus control unit, a program flow monitoring system and a method for program flow monitoring for a star topology, wherein troubleshooting in an application program is possible in a simple and cost-effective manner.
SUMMARY OF THE INVENTION
Accordingly, the present invention makes use of a multiplicity of address comparators for making a comparison between an address which is present in a particular case and a predefined address area, in which case a predefined data processing unit is deactivated and a data stream is mirror-imaged to the bus interface of the associated bus if the address which is present does not occur in the predefined address area. Data is also mirror-imaged onto a predefined bus even if it is not actually intended for this bus, for which reason it can be monitored by the program flow monitoring unit. However, because the data processing unit which is associated with the predefined bus is also deactivated, there is no unintended exchange of data between data processing units.
The data processing unit which is connected to the predefined bus is preferably a passive data processing unit and/or a data processing unit which is accessed jointly by the other data processing units. In particular, this predefined data processing unit is a common main storage.
The predefined data processing unit is preferably deactivated using a data processing unit selection signal with which the unit is switched into an inactive state.
The program flow monitoring system for a star topology is composed of the bus control unit described above, wherein a flow monitoring device for monitoring the data stream is connected to the predefined bus.
In the method for program flow monitoring in a star architecture, a predefined bus which is to be monitored is initially defined, and then an address area which is associated with this bus is defined. The addresses which are present at the various buses are then compared with the predefined address area. If the present address does not occur in the predefined address area, the predefined data processing unit which is connected to the predefined bus is deact
Herold Bernd
Hutner Franz
Bell Boyd & Lloyd LLC
Bonzo Bryce P.
Siemens Aktiengesellschaft
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