Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-11-08
2004-12-21
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S145000, C365S158000, C365S210130
Reexamination Certificate
active
06834018
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory device, in particularly to a magnetic random access memory (MRAM) device on which a data read operation is performed referring to a reference cell.
2. Description of a Related Art
In some cases, operation for reading data stored in a memory cell of a semiconductor memory device such as MRAM (Magnetic Random Access Memory) and FRAM (Ferroelectric Random Access Memory) is performed referring to a reference cell. For example, in the case of MRAM, the amount of current read from a memory cell and the amount of current read from a reference cell are compared to one another to identify data stored in the memory cell. Furthermore, in the case of FRAM, a voltage appearing on a reference bit line when a reference cell is connected to the reference bit line and a voltage appearing on a bit line when a memory cell is connected to the bit line are compared to one another to identify data stored in the memory cell.
FIG. 11
illustrates a memory cell array
101
of a MRAM of a related art. The memory cell array
101
includes word lines W
1
to W
m
(m: natural number, m>1) and bit lines B
1
to B
n
. (n: natural number, n>1) At individual positions at which the word lines W
1
to W
m
and the bit lines B
1
to B
n
intersect one another are disposed memory cells. The memory cell disposed at the position at which, the word line W
i
and the bit line B
j
intersect one another is denoted by a memory cell “C
ij
.”
FIG. 12
illustrates the structure of the memory cell C
ij
. The memory cell C
ij
includes a fixed layer
111
, a data storage layer
112
and a tunnel insulation film
113
. The fixed layer
111
is connected to the word line W
i
and the data storage layer
112
is connected to the bit line B
j
. Both the fixed layer
111
and the data storage layer
112
consist of a ferromagnetic material and respectively have a spontaneous magnetization. The tunnel insulation film
113
is disposed between the fixed layer
111
and the data storage layer
112
, and formed to have a film thickness for allowing tunnel current to flow between the fixed layer
111
and the data storage layer
112
. The film thickness of the tunnel insulation film
113
is typically 1.5 nm.
As shown in
FIG. 13
, the memory cell C
ij
stores data “0” or data “1” therein depending on directions of spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
. The direction of the spontaneous magnetization of the fixed layer
111
is being fixed. The direction of the spontaneous magnetization of the data storage layer
112
can freely be inverted and coincides with one of two directions, i.e., the same direction as that of the spontaneous magnetization of the fixed layer
111
and the direction reverse to that of the spontaneous magnetization thereof. When the directions of spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
coincide with each other, the spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
are denoted as “parallel” and when the directions of spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
are opposite each other, the spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
are denoted as “anti-parallel.” The memory cell C
ij
has one of “parallel” state indicating the directions of spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
are parallel to each other and “anti-parallel” state indicating the directions thereof are opposite each other, and an electrical state corresponding to the “parallel” state indicating the directions of spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
are parallel to each other is made to correspond to one of data “0” and data “1,” and an electrical state corresponding to the “anti-parallel” state indicating the directions thereof are opposite each other is made to correspond to the other of data “0” and data “1.” Hereinafter, explanation will be made assuming that an electrical state corresponding to the “parallel” state indicating the directions of spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
are parallel to each other corresponds to data “1,” and an electrical state corresponding to the “anti-parallel” state indicating the directions thereof are opposite each other corresponds to data “0.”
Data stored in the memory cell C
ij
is identified utilizing a change of resistance value of the tunnel insulation film
113
due to tunnel magneto-resistance effect (TMR effect). The resistance of the tunnel insulation film
113
varies depending on the states, i.e., the “parallel” state indicating the directions of spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
are parallel to each other, and the “anti-parallel” state indicating the directions thereof are opposite each other. That is, the first resistance of the tunnel insulation film
113
when the spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
are in the “anti-parallel” state is larger than the second resistance thereof when the spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
are in the “parallel” state by 10 to 40% of the second resistance. Thus, data stored in the memory cell C
ij
is identified utilizing a difference in resistance of the tunnel insulation film
113
.
Data stored in the memory cell C
ij
is read based on current flowing between the word line W
i
and the bit line B
j
. When the data stored in the memory cell C
ij
is read, a specific potential difference is applied between the word line W
i
and the bit line B
j
. The amount of current flowing between the word line W
i
and the bit line B
j
by applying the specific potential difference therebetween varies depending on the resistance of the tunnel insulation film
113
. Since the resistance of the tunnel insulation film
113
varies depending on the states corresponding to the directions of spontaneous magnetizations of the fixed layer
111
and the data storage layer
112
, the data stored in the memory cell C
ij
can be identified based on current flowing between the word line W
i
and the bit line B
j
.
In this case, the data stored in the memory cell C
ij
can be identified referring to a reference cell that has a structure similar to that of a memory cell. As shown in
FIG. 11
, the memory cell array
101
has reference cells R
1
to R
m
provided therein, each of which includes previously determined data written thereinto. The reference cells R
1
to R
m
all are connected to a reference bit line B
r
. The reference cells R
1
to R
m
are connected respectively to word lines W
1
to W
m
. Data stored in memory cells C
i1
to C
in
, which are connected to the word line W
i
, is read referring to the reference cell R
i
.
The reference cells R
1
to R
m
are designed so that current I(Ref) flowing through each of the reference cells R
1
to R
m
satisfies the following equation.
I(1)>I(Ref)>I(0) (1)
I(0): current flowing through a memory cell storing data “0”
I(1): current flowing through a memory cell storing data “1”
The data stored in the memory cell C
ij
is identified by comparing current flowing through the memory cell C
ij
and the current flowing through the reference cell R
i
with each other. When the memory cell C
ij
is identified, a specific potential difference is applied between the word line W
i
and the reference bit line B
r
to pass current through the reference cell R
i
. Furthermore, a specific voltage is applied between the word line W
i
and the bit line B
j
to pass current through the memory cell C
ij
. Furthermore, a specific potential difference is applied between the word line W
i
and the bit line B
j
to pass current through the memory cell C
ij
. The amount of current having flowed through the memory cell C
ij
and the amount of c
Okazawa Takeshi
Tahara Shuuichi
Ho Hoai
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
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