Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2002-01-09
2004-08-31
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C712S216000
Reexamination Certificate
active
06785779
ABSTRACT:
BACKGROUND OF THE INVENTION
Technical Field
The invention relates to a method of maintaining memory coherence and consistency in a computer system by classification of transaction address conflicts to improve efficiency in multi-node systems utilizing snoopy cache architecture.
BACKGROUND OF THE RELATED ART
Computer systems which utilize multiple microprocessors and distributed memory resources across two or more nodes in the system utilize snoopy cache-based systems to maintain transaction ordering throughout the system, including tracking location of data which may be stored on one or more nodes of the system. In such snoopy cache-based systems, the order in which data transactions are allowed to proceed through the system is essential in maintaining memory coherency and consistency across the system. The simplest form of maintaining such coherency and consistency is simply ensuring that no transactions in the system can pass each other so that proper data processing ordering is maintained That is, if a transaction in the system cannot be started until the previous trasaction is completed, this simple technique enforces this order requirement.
Other systems have increased efficiency by restricting the ordering of the timing of transactions to only transactions with the same address or address index so that they do not pass each other in the system when processing. One problem with maintaining data ordering is that whenever transactions block each other, the performance of the system is naturally degraded because of the delays inherent with the transaction which may be waiting to proceed.
In a two-level snoopy cache architecture in a multi-processing system, the number of memory control devices or agents generating potentially conflicting addresses throughout the system is increased further, making efficient handling of the conflicts even more important. It is desirable, therefore, to enhance the address ordering flow by selection and implementation of an efficient set of ordering rules which prioritize or reorder potentially conflicting or actual conflicting addresses arising from ongoing system transactions such as to allow optimization of the system's capabilities and increase system speed by minimizing the impact of conflicting addresses issued by a memory control agent.
SUMMARY OF THE INVENTION
The invention is useful in multiprocessor computing systems having multiple, interconnected nodes, with each node having a local memory device and a processor device for accessing data from both the node's local memory device and the local memory device of another node.
A first aspect of the invention is a method for executing first-in-time and second-in-time transactions to be executed by the processors of such a system. The transactions are classified based at least in part on location of data to be accessed during their execution, and an execution dependency criterion is selected based on those classifications. Depending on the execution dependency criterion, the second in time transaction is deferred, and later released depending further on execution of the first in time transaction as it related to the criterion. The execution dependency criterion preferably releases the second in time transaction either: after the first in time transaction is placed in an ordered processor bus queue; after the first in time transaction is placed in an ordered memory queue; or after all dependencies of the first in time transaction are released.
Another aspect of the invention is an article such as a computer program product executable in a computer system as outlined above. The article comprises classifications of first-in-time and second-in-time transactions at least partly based on location of data to be accessed during execution of the transactions. The article also includes an execution dependency criterion based on the classifications, a deferral of the second-in-time transaction based on the criterion; and a release of the second-in-time transaction for execution at least partly based on the criterion and on execution of the first in time transaction.
Yet another aspect of the invention is in a multiprocessor computer system itself. The system includes multiple, interconnected nodes, each having at least one local memory device and at least one processor device capable of accessing data from both the local memory device of said node and the local memory device of another node. Classifications of first-in-time and second-in-time transactions in the system are based at least in part on location of data to be accessed during execution of the transaction. The system includes a deferred execution queue for the second-in-time transaction based on an execution dependency criterion which is based at least partly on the classifications. The system also includes a release of the second-in-time transaction for execution by a processor based at least in part on the criterion and on execution of the first in time transaction by the same or another processor. The system preferably further comprises a central hardware device interconnecting the nodes and storing information regarding location of data within the system, and both cache and main memory at each of the nodes.
Other features and advantages of the invention will become apparent from the following detailed description of its presently preferred embodiment, taken in conjunction with the accompanying drawings.
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Berg Thomas B.
Lloyd Stacey G.
International Business Machines Company
Law Offices of Michael Dryja
Moazzami Nasser
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