Mask repattern process

Details Mask repattern process Mask repattern process

2003-04-25

2004-11-09

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S640000

Reexamination Certificate

active

06815327

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of repatterning circuits and the like on semiconductor devices. More specifically, the present invention relates to a method for forming conductive bumps on a die for flip-chip type attachment to a printed circuit board, or the like, after the repatterning of a circuit on a semiconductor device. In particular, the present invention relates to a method for forming under bump metallization pads, which method utilizes simplified or a minimal number of masking steps.
2. State of the Art
The following terms and acronyms will be used throughout the application and are defined as follows:
BGA—Ball Grid Array: An array of minute solder balls disposed on conductive locations of an active surface of a semiconductor die, wherein the solder balls are refluxed for simultaneous attachment and electrical communication of the semiconductor die to conductors of a printed circuit board or other substrate.
A chip or die that has a pattern or array of terminations spaced around the active surface of the die for face-down mounting of the die to a substrate.
A method of attaching a semiconductor die to a substrate in which the die is inverted so that the connecting conductor pads on the face of the device are set on mirror-image pads of conductive traces carried by the substrate and bonded thereto by solder reflux. Also, sometimes known as C4 attachment (“Controlled Collapse Chip Connection”).
SLICC—Slightly Larger than Integrated Circuit Carrier: An array of minute solder balls disposed on an attachment surface of a semiconductor die similar to a BGA, but having a smaller solder ball diameter and pitch than a BGA.
High performance microelectronic devices may comprise a number of flip-chips having a BGA or a SLICC attached to a ceramic or silicon substrate or printed circuit board (“PCB”) such as an FR4 board for electrical interconnection to other microelectronic devices. For example, a very large scale integration (“VLSI”) chip may be electrically connected to a substrate, printed circuit board, or other next higher level packaging carrier member using solder balls or solder bumps. This connection technology may be referred to generically as “flip-chip” or “C4” attachment.
Flip-chip attachment requires the formation of contact terminals at flip-chip contact sites on the semiconductor die, each site consisting of a metal pad with a lead/tin solder ball formed thereon. Flip-chip attachment also requires the formation of solder joinable sites (“pads”) on the metal conductors of the PCB or other substrate or carrier which are a mirror-image of the solder ball arrangement on the flip-chip. The pads on the substrate are usually surrounded by non-solderable barriers so that when the solder balls of the chip contact sites are aligned with the substrate pads and “reflow,” the surface tension of the liquified solder element supports the semiconductor chip above the substrate. After cooling, the chip is essentially welded face down by very small, closely spaced, solidified solder interconnections. An underfill encapsulant is generally disposed between the semiconductor die and the substrate for environmental protection and to further enhance the mechanical attachment of the die to the substrate.
FIGS. 1
a-h
show a contemporary, prior art method of forming a conductive ball arrangement on a flip-chip. First, a plurality of semiconductor devices, such as dice including integrated circuitry (not shown), is fabricated on a face surface
12
of a semiconductor wafer
10
. A plurality of conductive traces
14
is then formed on the semiconductor wafer face surface
12
, positioned to contact circuitry of the respective semiconductor elements (not shown), as in
FIG. 1
a
. A passivation film
16
, such as at least one layer of SiO
2
film, Si
3
N
4
film, or the like, is formed over the semiconductor wafer face surface
12
as well as the conductive traces
14
, as shown in
FIG. 1
b
. A first layer of etchant-resistive photoresist film
18
is subsequently applied to a face surface
20
of the passivation film
16
. The first photoresist film
18
is next masked, exposed, and stripped to form desired openings (one illustrated) in the first photoresist film
18
. The passivation film
16
is then etched through the opening in photoresist film
18
to form a via
22
with either sloped edges or walls
26
, or even substantially vertical walls, and which exposes a face surface
24
of the conductive trace
14
, as shown in
FIG. 1
c
. First photoresist film
18
is then stripped, as shown in
FIG. 1
d.
FIG. 1
e
shows metal layers
28
,
30
, and
32
applied over the passivation film face surface
20
as well as the via
22
to form a multi-layer under bump metallurgy (UBM)
34
by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), either sputtering or evaporation. The metal layers usually comprise chromium for the first or base adhesion layer
28
, chromium-copper alloy for a second, intermediate layer
30
, and copper for the third, outer soldering layer
32
. Additionally, a fourth metal layer (not shown) of flashed gold is occasionally placed atop the copper third layer
32
to prevent oxidation of the copper. Nickel, palladium, and platinum have also been employed as the outer or soldering layer
32
. Furthermore, titanium or titanium/tungsten alloys have been used as alternatives to chromium for the adhesion layer. Two-layer UBMs with a gold flash coating are also known, as are single-layer UBMs.
A second layer of etchant-resistive photoresist film
35
is then masked, exposed, and stripped to form at least one second etchant-resistive block
36
over the vias
22
, as shown in
FIG. 1
f
. The metal layers
28
,
30
, and
32
surrounding vias
22
are then etched and the etchant-resistive block
36
is stripped to form a discrete UBM pad
40
, as shown in
FIG. 1
g
. A solder bump
42
is then formed on the UBM pad
40
, as shown in
FIG. 1
h
, by any known industry technique, such as stenciling, screen printing, electroplating, electroless plating, evaporation or the like.
The UBM pads
40
can also be made by selectively depositing the metal layers by evaporation through a mask (or photoengraving) onto the passivation film face surface
20
as well as the via
22
such that the metal layers
28
,
30
, and
32
correspond to the exposed portions of the conductive traces
14
.
Solder balls are generally formed of lead and tin. High concentrations of lead are sometimes used to make the bump more compatible with subsequent processing steps. Tin is added to strengthen bonding (to such metal as copper) and serves as an antioxidant. High-temperature (melting point of approximately 315 degrees Centigrade) solder alloy has been used to join chips to thick ceramic substrates and multi-layer coffered ceramic interface modules. Joining chips to organic carriers, such as polyamide-glass, polyamide-aramid, and the like, as well as the printed wiring boards, requires lower temperatures which may be obtained by using 63Sn/37Pb solder (melting point 183 degrees Centigrade) and various Pb/In alloys, such as 50Pb/50In (melting point of approximately 220 degrees Centigrade). Lower melting point alloys (down to 60 degrees Centigrade) have been used to bump very temperature-sensitive chips, such as GaAs and superconducting Josephson junctions.
Numerous techniques have been devised to improve the UBM and formation of solder bumps for flip-chips. For example, U.S. Pat. No. 4,360,142, issued Nov. 23, 1982, to Carpenter et al., relates to forming multiple layer UBM pads between a semiconductor device and a supporting substrate particularly suited to high stress use conditions that generate thermal gradients in the interconnection.
U.S. Pat. No. 5,137,845, issued Aug. 11, 1992, to Lochon et al., pertains to a method of forming solder bumps and UBM pads of a desired size on semiconductor chips based on an involved photolithographic technique such that the dimensions of t

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