Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2001-08-16
2004-10-05
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S095000, C326S098000
Reexamination Certificate
active
06801057
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of logic circuits and more specifically to a novel design methodology for achieving faster circuits with a more compact circuit layout.
BACKGROUND OF THE INVENTION
Designing small, fast, low-power, and reliable logic circuits is becoming more difficult with scaling. Integrated logic circuits on silicon on insulator (SOI) substrates are beginning to find increasing usage in an effort to achieve these goals. SOI refers to a silicon substrate where the top layer (in which the devices are fabricated) is separated from the “bulk” portion of the substrate by a insulator layer. This can be contrasted with bulk silicon substrates which have no buried insulator layer. In bulk CMOS circuits, NMOS transistors are fabricated in p-type wells and PMOS devices are formed in n-type wells with both well structures formed in the substrate. These well structures provide the electrical isolation required between the NMOS and PMOS transistors in CMOS logic circuits. The spacing requirement of these well structures for proper electrical isolation in bulk CMOS logic circuit fabrication has led to grouping of NMOS and PMOS transistors to maximize circuit density. In bulk CMOS circuits, basic transistor networks performing logic functions can be classified as the following three types: pull-up network (PUN), which conditionally forms a current path between the output node and the circuit power supply, pull-down network (PDN), which conditionally forms a current path between the output node and the circuit ground, and pass-transistor network (PTN), which conditionally forms a current path between the output node and the pass inputs. In general only PMOS transistors are used in a PUN, only NMOS transistors are used in a PDN, and only PMOS or only NMOS transistors are used in a PTN. In early NMOS logic circuits, both enhancement and depletion mode NMOS transistors were used as pull up devices. In these NMOS circuits however, the gate of the enhancement transistor was connected to a fixed voltage (usually the supply voltage) and the gate of the depletion transistor was connected to the output node.
In general, digital circuits can be divided into two groups, static and dynamic circuits. Dynamic circuits can be further subdivided into one-phase “domino” circuits, two-phase ratioed, and ratioless circuits. Ratioless dynamic circuits can be further divided into two-phase and four-phase circuits. Logic networks generally comprise combinational and sequential networks. Combinational networks comprise gates and programmable logic arrays, and sequential networks comprise latches, registers, counters, and read-write memory. Combinational logic networks operate without the need of any periodic clock signals. However all but the very smallest digital systems require sequential as well as combinational logic. As a practical matter, all systems employing sequential logic require the use of periodic clock signals for correctly synchronized operation. In static SOI logic circuits, combinational or sequential, clock signals are introduced only at normal gate inputs, identical to those used for logic inputs. In applications where circuit delay is important and where silicon area is at a premium, CMOS dynamic logic circuits are used. Dynamic gates require clock signals that perform a precharge function to reduce circuit delay.
Conventional SOI logic circuits are based on bulk CMOS logic with conventional SOI circuits and bulk CMOS circuits sharing the same circuit topology. Thus in conventional SOI logic circuits, only PMOS transistors are used in a PUN, only NMOS transistors are used in a PDN, and only PMOS or only NMOS transistors are used in a PTN. This circuit layout and design methodology while optimized for bulk CMOS circuits does not take full advantage of the unique properties of SOI substrates. A new circuit design methodology is therefore required that fully utilizes the properties of SOI substrates for CMOS logic circuits.
SUMMARY OF THE INVENTION
The instant invention is a dynamic logic circuit on a SOI substrate, comprising: a pull-down network comprising a plurality of series connected MOS transistors wherein at least one of said plurality of series connected MOS transistors is a NMOS transistor and at least one of said plurality of series connected MOS transistors is a PMOS transistor; a precharge circuit connected to a clock signal, a circuit supply voltage, and said pull-down network; a ground switch circuit connected to said clock signal and to said pull-down network; and an output node which is connected to a common node of said pull-down network and said precharge circuit. In addition, the precharge circuit comprises a PMOS transistor; the ground switch circuit comprises a NMOS transistor; and at least one of said MOS transistors in said pull-down network has a gate tied to a floating substrate body.
Other embodiments of the instant invention comprises: a pull-down network comprising a plurality of parallel connected MOS transistors with a first and second common node, wherein at least one of said plurality of parallel connected MOS transistors is a NMOS transistor and at least one of said plurality of parallel connected MOS transistors is a PMOS transistor; a precharge circuit connected to a clock signal and to said first common node of said pull-down network; a ground switch circuit connected to said clock signal and to said second common node of said pull-down network; and an output node which is connected to said first common node of said pull-down network.
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patent: 2001/0001229 (2001-05-01), Hagihara
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Chang Daniel D.
Texas Instruments Incorporated
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