Method and apparatus for a dynamic, multi-speed bus architecture

Details Method and apparatus for a dynamic, multi-speed bus architecture Method and apparatus for a dynamic, multi-speed bus architecture

1993-03-16

1996-04-16

Harvey, Jack B.

395286, B06F 1314

Patent

active

055091261

ABSTRACT:
A dynamic, multi-speed bus architecture comprising a plurality of variable speed, fixed size links for coupling a plurality of devices together in an arbitrary network arrangement in which each device coupled to the bus comprises a novel communications node having a scalable interface for enabling the local hosts of the devices to communicate via the multi-speed bus. The interface provided within each node comprises a first module and a second module interconnected via a fixed speed, variable size bus. The first module is coupled to the local host of a device via a fixed speed, fixed size bus for converting a first data packet received from the local host into a second data packet of an appropriate form for transmission on the fixed speed, variable size bus disposed between the two modules. The second module receives the second data packet and converts it into a third data packet of an appropriate form for transmission onto the variable speed, fixed size link coupling the device to the multi-speed bus. The first and second modules further perform the same conversions in reverse so as to provide for reception of data packets transferred on the multi-speed bus. With such a design of the interface disposed between the link of the multi-speed bus and the local host of each device, it is possible to provide the components for performing the data packet transfer conversions necessary to realize a true dynamic, multi-speed bus in addition to providing a truly scalable architecture having upward compatibility with future devices.

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