Method of operating a vertical DMOS transistor with schottky...

Details Method of operating a vertical DMOS transistor with schottky... Method of operating a vertical DMOS transistor with schottky...

2000-09-12

2004-08-31

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S339000, C257S341000, C257S471000, C257S476000

Reexamination Certificate

active

06784489

ABSTRACT:

TECHNICAL FIELD
This invention relates to power MOS (DMOS) transistors, and more particularly, to a Schottky diode incorporated in parallel with an intrinsic body diode of a DMOS transistor to reduce parasitic effects.
BACKGROUND OF THE INVENTION
Power MOS transistors, also called DMOS transistors, are commonly used to drive inductive loads such as solenoids or DC motors. A DMOS transistor can transfer peak currents of up to 280 amps or continuous currents of up to 70 amps to an inductive load. The DMOS transistor may operate at voltages as high as 1,000 volts with a resistance as low as 0.02 ohms. The DMOS transistor is also not susceptible to thermal runaway or secondary breakdown problems.
DMOS transistors are typically fabricated in an IC chip which is connected to control the inductive load. The semiconductor structure of the DMOS transistor gives rise to parasitic effects which, under the appropriate conditions, may degrade the performance of the transistor. Specifically, body diodes, parasitic bipolar junction transistors (BJTs) and capacitances influence the operation of the DMOS transistor.
The parasitic effects may be illustrated with reference to a conventional H-bridge circuit shown in FIG.
1
. An inductive load L is powered by four N-channel DMOS transistors, M
1
, M
2
, M
3
, and M
4
. A drain of the transistor M
2
and a drain of the transistor M
3
are connected to a voltage source Vcc. A source of the transistor M
4
and a source of the transistor M
1
are drain of the transistor M
4
are connected to a first end of the inductive load L, and a source of the transistor M
3
and a drain of the transistor M
1
are connected to a second end of the inductive load L. Each of the DMOS transistors is shown with a respective body diode Db
1
, Db
2
, Db
3
, and Db
4
connected between the source and the drain. The body diode is intrinsic to the structure of the DMOS transistor. Parasitic transistors QP and QP
2
are also shown.
The four DMOS transistors of the H-bridge circuit control the delivery of current to the inductive load L. The DMOS transistors are alternately switched on and off to permit current to flow from the voltage source Vcc to the ground voltage reference. For example, when the transistors M
1
and M
2
are switched on and the transistors M
3
and M
4
are switched off, current will flow from the voltage source Vcc, through the transistor M
2
, the inductive load L, and the transistor M
1
to the ground voltage reference. If the transistors M
3
and M
4
are switched on, and the transistors M
1
and M
2
are switched off, current will flow from the voltage source Vcc through the transistor M
3
, the inductive load L, and the transistor M
4
to the ground voltage reference.
When the DMOS transistors switch on or off to change the direction of current in the inductive load L, the inductive load L will react by applying a transient voltage to oppose the changing current. The transient voltage will often activate the parasitic devices in the DMOS transistor. For example, with reference to
FIG. 1
, if the transistors M
3
and M
4
are conducting current through the inductive load L and are switched off, the inductive load L will react to maintain the current. Specifically, the drain of the transistor M
1
will be driven below the ground voltage reference to draw current through the transistor M
1
, and the source of the transistor M
2
will be driven above the voltage source Vcc to force current through the transistor M
2
. The parasitic effects may be demonstrated by examining the structure of the DMOS transistor.
A cross-sectional view of a conventional N-channel DMOS transistor
8
of the type used for the transistors M
1
-M
4
is shown in FIG.
2
. It has gate G, source S, and drain D, terminals as shown as well as a parasitic PNP transistor QP
2
and a body diode Db. The structure of DMOS transistor
8
may be provided by a method known to those skilled in the art.
The body diode Db is comprised of a P
+
type body region
10
and an N type epi pocket
12
. The body diode Db is intrinsic to the structure of the DMOS transistor
8
and has a turn-on threshold voltage and a series resistance. The parasitic PNP transistor QP
2
is comprised of the P
+
body region
10
acting as an emitter, an N
+
type drain region
14
and the epi pocket
12
acting as a base, and a P
−
type substrate
16
acting as a collector. A finite resistance in the P
−
substrate
16
is represented by a resistor Rsub. A P
+
type region
18
links the P
−
substrate
16
with a ground voltage reference at a surface of the P
−
substrate
16
. A second N type epi pocket
20
is shown in the P
−
substrate
16
to support a separate device.
The known DMOS transistor
8
operates as follows. When a voltage at the drain terminal D exceeds a voltage at the source terminal S, and a positive voltage is applied to the gate terminal G which exceeds a threshold voltage of the DMIOS transistor
8
, current flows from the drain terminal D and the N
+
drain region
14
to two N
+
type source regions
22
and
24
through N type channels induced in the P
+
body region
10
. When the voltage applied to the gate terminal G falls below the threshold voltage, the transistor is turned off and current through the DMOS transistor
8
stops.
The body diode Db and the parasitic PNP transistor QP
2
may be activated when a voltage applied to the source terminal S of the DMOS transistor
8
exceeds a voltage at the drain terminal D of the DMOS transistor
8
. This is called an oversupply effect. If the voltage at the source is sufficiently high, the body diode Db will be forward biased, and a recirculation current will flow from the source terminal S, through the P
30
body region
10
, the epi pocket
12
, and the N
+
drain region
14
to the drain terminal D. When the parasitic PNP transistor QP
2
is activated, a portion of the current from the source terminal S will flow through the emitter, the base, and into the P
−
substrate
16
acting as the collector of the transistor QP
2
.
The efficiency of the transistor QP
2
may be reduced by surrounding the DMOS transistor
8
with an N
+
type region which, together with a buried N
+
type layer, will act as a highly doped base so that only a small faction of the current from the source terminal S (usually 3 to 4%) may reach the P
−
substrate
16
. The current into the P
−
substrate
16
raises the potential of the substrate because it has a finite resistance Rsub. The epi pockets
12
and
20
have a voltage close to the voltage of the P
−
substrate
16
which enhances the effect of this current. A rising potential in the P
−
substrate
16
may forward bias junctions between the P
−
substrate
16
and the epi pockets
12
and
20
, and consequently inject current into the epi pockets
12
and
20
. Such current injection is highly undesirable. A conventional method of alleviating the effect is to connect the P
−
substrate
16
to a ground reference potential. However, this solution exacerbates another parasitic effect known as the below ground effect.
The below ground effect is described with reference to a cross-sectional view of the conventional N-channel DMOS transistor
8
shown in FIG.
3
. The structure of the DMIOS transistor
8
is identical to that of the DMOS transistor
8
shown in
FIG. 2
, and equivalent regions and elements have been given the same reference numerals. In addition to the regions and elements shown in
FIG. 2
, two N type epi pockets
26
and
28
support other devices located near the DMOS transistor
8
in the P
−
substrate
16
. Each of the epi pockets
20
,
26
, and
28
receive a device current IcP. A parasitic, bulk distributed NPN transistor QP is shown having the epi pocket
12
and the N
+
drain region
14
acting as an emitter, the P
−
substrate
16
and the P
+
region
18
acting as a base, and each of the epi pockets
20
,
26
, and
28
acting as co

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