Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2003-03-27
2004-08-03
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S692000, C438S733000, C438S734000, C438S182000, C438S574000
Reexamination Certificate
active
06770552
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to a semiconductor device such as a field effect transistor having a gate electrode structure with a metal silicide layer formed thereon.
2. Description of the Related Art
Generally, a silicon-based field effect transistor comprises highly doped silicon regions, also referred to as drain and source regions, that are embedded in a lightly and inversely doped silicon region, a so-called N-well or P-well, depending on the type of transistor. The drain and the source regions are spaced apart by a channel region interposed therebetween, wherein a conductive channel forms between the drain and source regions in the channel region upon application of an appropriate voltage to a gate electrode that is usually formed over the channel region and is separated therefrom by a gate insulation layer, often provided as a gate oxide layer.
Thus, in the most common field effect transistors, the gate electrode structure essentially comprises the gate electrode formed above the gate insulation layer, with polysilicon often being selected as the material for forming the gate electrode for several reasons.
For instance, polysilicon exhibits high compatibility with the subsequent high temperature processes that will be performed in completing the manufacture of the integrated circuit device. Moreover, the polysilicon interface with thermal silicon dioxide is well understood and electrically stable. Furthermore, polysilicon is more reliable than, for example, aluminum gate materials, and can be deposited conformally over a step-like topography. However, problems arise when polysilicon is used as a gate electrode material due to its higher electric resistance compared to metals, such as aluminum. Even when doped at the highest practical concentration, a 0.5 &mgr;m thick polysilicon film has a sheet resistance of about 20 &OHgr;sq. compared to 0.05 &OHgr;sq. for a 0.5 &mgr;m thick aluminum film. The resulting high values of interconnect line resistance can therefore lead to relatively long RC time constants (i.e., long propagation delays) and DC voltage variations within VLSI (very large scale integration) circuits.
To overcome this drawback, several solutions have been proposed and developed in the art. Among these solutions, the formation of metal silicides on the top of the polysilicon gate structure has proven to be the most reliable one for obtaining the lowest resistance values.
A typical prior art method of forming metal silicides on silicon-containing regions, such as the gate electrode of a MOS transistor, will be described in the following with reference to
FIGS. 1
a
-
1
d.
FIG. 1
a
schematically shows a MOS transistor
100
to be formed on a substrate
1
, such as a silicon wafer. Isolation structures
2
define an active region of the transistor
100
. Moreover, reference
3
relates to a polysilicon gate electrode of the MOS transistor
100
. Reference
4
relates to oxide side spacers formed on the sidewalls of the polysilicon gate electrode
3
. Reference
6
denotes a gate insulation layer and reference
5
relates to the source and drain regions of the MOS transistor
100
.
FIG. 1
b
shows the MOS transistor
100
with a refractory metal layer
7
deposited thereon. In
FIG. 1
c
, reference
8
relates to metal silicide layers formed on top of the polysilicon gate electrode
3
and on the source and drain regions
5
.
Starting with the MOS transistor as depicted in
FIG. 1
a
, in a first step, the refractory metal layer
7
is deposited on the MOS transistor
100
, as depicted in
FIG. 1
b
. Usually, either titanium or cobalt is used as a metal for forming the metal layer
7
, and typically a physical vapor deposition (PVD) process, e.g., a sputtering process, is carried out for depositing the refractory metal layer
7
.
Once the refractory metal layer
7
has been deposited, a low temperature thermal step (approximately 450° for copper or 650° for titanium, respectively) is carried out to react the metal in contact with silicon on the source/drain regions
5
and the polysilicon gate electrode
3
. During the thermal step, inter-diffusion of the polysilicon and metal occurs at the polysilicon/metal interface on top of the polysilicon gate electrode
3
as well as on the source/drain regions
5
. As a result, the metal silicide layers
8
are formed as depicted in
FIG. 1
c
, whereby the refractory metal layer
7
is at least partially consumed.
In a subsequent step, as depicted in
FIG. 1
d
, the non-reacted metal is selectively removed with a selective wet-etching step, leaving behind the metal suicide layers
8
on top of the silicon gate electrode
3
and on the source/drain regions
5
.
Commonly, a further heat treatment (not depicted in the figures) is carried out at a higher temperature than the previous heat treatment to transform the metal silicide layers
8
into a more stable phase that exhibits a lower resistance than the metal silicide layers formed during the previous lower temperature heat treatment. For example, if cobalt is used, a cobalt mono-silicide is formed during the first heat treatment, which is then converted into a cobalt disilicide.
Since the finally-obtained metal silicide layers
8
exhibit a sheet resistance that is much lower compared to the sheet resistance of polysilicon, the total resistance of the gate electrode
3
including the metal silicide layers
8
is decreased.
The prior art method described above has accomplished satisfactory results for devices having minimum feature sizes of 0.5 &mgr;m and more. The above method, however, is not completely adequate to compensate for the increase of the polysilicon sheet resistance which arises in the case of deep-sub-micron devices, i.e., with feature sizes equal to or smaller than 0.25 &mgr;m.
The reasons for this can be explained as follows. As a general rule, decreasing the transistor size, i.e., the channel length, that is, in
FIGS. 1
a
-
1
d
, the horizontal distance between the source/drain regions
5
, requires reducing the thickness of the gate insulation layer
6
and necessitates shallower source/drain regions which, in turn, restrict the achievable thickness of the metal silicides
8
. As the metal silicide layer
8
for the gate electrode
3
is simultaneously formed with the metal silicide layers
8
of the drain and source regions
5
, the thickness and, thus, the reduction in resistance, of the gate silicides is also restricted.
As the cross-sectional dimensions of the polysilicon gate electrode
3
decrease as a result of the continuous miniaturization of the devices, the resistance of the polysilicon portions of the gate structures increases and represents the dominant contribution of the resistance of the polysilicon gate electrode
3
. The final, total resistance of the gate electrodes is, therefore, only scarcely influenced by the silicide layer but practically corresponds to the resistance of the polysilicon portion of the gate structure.
Since the trend toward an increasing miniaturization of the devices manufacturable on a substrate will continue in years to come, it clearly results that the formation of metal silicide layers on the top of gate polysilicon lines according to the prior art methods will render it very difficult to realize gate structures featuring resistances in conformity with the electrical performance required.
Accordingly, in view of the problems explained above, it would be desirable to provide a technique that may solve or reduce one or more of the problems identified above.
SUMMARY OF THE INVENTION
In general, the present invention is based on the consideration that gate structures featuring a low sheet resistance can be realized by “decoupling” the effective gate length from the gate resistance in that the cross-sectional area of polysilicon lines is increased in an upper portion that is at least partially silicided, while the desired bottom-CD (bottom critical dimension) of the lines is maintained
Horstmann Manfred
Stephan Rolf
Wieczorek Karsten
Advanced Micro Devices , Inc.
Williams Morgan & Amerson P.C.
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