Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-10-01
2004-06-15
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C073S514220, C216S002000, C216S061000, C216S086000, C438S017000, C438S719000, C438S008000
Reexamination Certificate
active
06750152
ABSTRACT:
TECHNICAL FIELD
This invention relates to an apparatus and method for testing batch formed microelectronic devices to determine whether or not the batch forming methodology has been effectively carried out.
BACKGROUND OF THE INVENTION
Microelectronic circuit devices are typically batch formed by, for example, discretizing the locations and geometry of said devices in an essentially continuous layer of semiconductor material and thereafter exposing the discretized semiconductor material to a forming medium which removes material from the semiconductor layer except where it is protected by an etchant resistant material commonly called “photoresist.” A representative forming process is known as inductively coupled plasma deep reactive ion etching (ICP DRIE) in which the forming medium is a reactive plasma. Removal of the semiconductor material by the etchant is essentially a trenching process which begins on one surface of the semiconductor material and progresses through the material at a rate which is dependent upon a number of factors, including the width of the trench. The fact that the etch process progresses at different rates for different gap widths is a phenomenon known as “etch lag” and must be addressed any time devices with different gap widths in their geometry are to be formed in a batch forming process such as ICP DRIE.
One environment in which the etch lag phenomenon is encountered is in the batch forming of micro-electro-mechanical systems commonly referred to as MEMS. MEMS devices include, by way of example, micro-mechanical filters, pressure sensors, gyroscopes, resonators, actuators, rate sensors, and accelerometers. A typical MEMS device is fabricated in large numbers by batch etching a semiconductor layer. The geometry of MEMS devices is typically such that a reasonably high level of accuracy is needed in maintaining the proper trench widths or gap sizes between the structural elements thereof so that electrical and/or mechanical interactions or effects between adjacent semiconductor structures are within acceptable levels. It is particularly important that adjacent semiconductor structures which are separated and electrically isolated from one another by a minimum width gap are in fact fully formed; i.e., it is important that the trench which forms the gap is etched through the appropriate semiconductor layer so that a short circuit does not occur between the two adjacent semiconductor structures, and so that mechanical structures are completely separated. Because of the etch lag phenomenon described above, it is possible in a batch etching process that the wider isolation gaps will be fully formed while narrower structural trenches in the device are not fully formed and that electrical short circuits or mechanical connections as described above will occur.
Many MEMS devices involve etch trenching or gap formation through a portion of semiconductor material which is suspended in part over a cavity so as to create the potential for physical movement between closely adjacent portions of the semiconductor structure. By way of example, an accelerometer may require the semiconductor layer at each device location to be etched in such a way as to form a linear or radially disposed array of essentially parallel narrow fingers of semiconductor material which are supported at one end, for example, on an oxide base but which extend from the oxide base out over a cavity in a cantilevered fashion. The structure of such a device is described in greater detail in the related application identified above, the disclosure of which is incorporated herein by reference.
Where a number of long parallel trenches are to be etched through the semiconductor material over a cavity, another phenomenon can affect the electrical properties of the semiconductor structures formed by etching. To explain, a wide trench designed for either electrical or structural isolation may form earlier than nearby narrow trenches in the etch process as a result of the etch lag phenomenon described above. Once the wider trench is fully formed, the etchant can fill the cavity and, because it is highly active, begin eroding the bottoms of the long fingers of semiconductor material which overlie the cavity. This undesirable etch can change finger bottom geometry from a relatively thick rectangular structure to one which begins to resemble a knife-edge, i.e., the edges of the fingers at or near the bottoms begin to erode inwardly from the corners. As this erosion continues, the electrical resistance of a finger of semiconductor material increases while the capacitive coupling between adjacent fingers may decrease.
In the past it has been customary to evaluate the qualities of the individual semiconductor devices and particularly their electrical characteristics by sacrificing an entire semiconductor wafer. To explain, wafers may be drawn at random from the manufacturing process and cut through so as to be prepared for either visual or machine assisted inspection. While this is wasteful of materials and manufacturing efficiency, it is preferable to separating the devices from the etched wafer and installing them in individual packages which are later found to be faulty.
SUMMARY OF THE INVENTION
According to the present invention, electronic devices such as, but not limited to, MEMS which are batch formed from an essentially continuous layer of semiconductor material may be tested to evaluate the effectiveness of the batch forming medium without sacrificing entire wafers.
In general this is accomplished through the steps of:
A. forming electrical test probe contacts in test sites;
B. discretizing, such as by application of a photoresist pattern layer, the locations and geometry of the devices in the semiconductor material layer wherein the geometry includes the definition of one or more gaps in the material layer which affect the electrical and/or mechanical properties of the devices;
C. discretizing one or more test sites in the semiconductor layer so as to include at least one gap which is dimensionally representative of a gap in the device geometry; thereafter
D. subjecting the layer to the forming medium; and
E. measuring at least one electrical property associated with the test site gap by probing the contacts described above.
The term “discretizing”, as used herein, typically refers to the application and selective removal of photoresist to a surface of the semiconductor layer prior to exposing the layer to the etchant thereby to define those areas of the semiconductor layer where the etchant will trench through the material from the exposed side toward the other side. While this is the typical definition, Applicants intend this term to cover any and all known and future developed methods for creating the two-dimensional pattern which is ultimately desired in the semiconductor structure.
Furthermore, it is to be understood that, according to the present invention, steps (A), (B), and (C) can be performed in any desired order before performing step (D).
The method of the present invention can be applied as hereinafter described to the manufacture of MEMS devices in large quantities in wafers or sheets of semiconductor material which are fully bonded to a substrate as well as wafers or sheets which have cavities formed beneath the semiconductor layer. The test probe contacts may be arranged so as to permit the testing in the test sites of either or both of capacitance and resistance.
In one embodiment hereinafter described, the test site comprises a linear array of contacts separated by test site gaps which vary from one another in a systematic way; e.g., the gaps vary in width from one another by a fixed difference increment and define a range from a minimum value which is at or below the minimum gap width to a maximum value which is at or in excess of an isolation gap width such that the gaps in the devices to be batch formed all fall within the test site range whether or not they correspond exactly to any of the gap values in the range. Alternatively the gaps in the test site may be selected to corresp
Chase Troy Allan
Christenson John Carl
Freeman John Emmett
Healton Robert Lawrence
Staller Steven Edward
Delphi Technologies Inc.
Funke Jimmy L.
Powell William A.
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