Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2002-04-10
2004-08-31
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S189090, C365S233100, C365S230010
Reexamination Certificate
active
06785157
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having memory cells storing data in capacitors.
2. Description of the Background Art
In a data processing field and the like, a circuit device called a system LSI (large-scale integrated circuit), wherein a memory device and a logic such as a processor are integrated in the same semiconductor chip, has been widely used in order to process data at a high speed with low power consumption. In the system LSI, the logic and the memory device are interconnected through on-chip interconnect lines. Therefore, the system LSI has the following advantages: (1) since the load of the signal interconnection lines is smaller than that of on-board interconnection lines, data/signals can be transmitted at a high speed; (2) since the number of pin terminals is not limited, the number of data bits can be made large so that the band width in transmitting data can be widened; (3) since the constituent elements are integrated on the semiconductor chip, the system scale can be reduced to implement a down-sized and light system, as compared to the configuration wherein discrete elements are arranged on a board; and (4) a macro prepared as a library can be arranged as a component formed on a semiconductor chip, and the efficiency of design is improved.
For the above-mentioned reasons, system LSIs are widely used in various fields. As a memory device to be integrated in the system LSI, there are used a DRAM (dynamic random access memory), an SRAM (static random access memory), and a flash type EEPROM (electrically erasable read only memory). As the logic, a processor for performing control and processing, an analogue processing circuit such as an A/D converting circuit, a logic circuit for performing a dedicated logic processing and such are used.
In the case that a processor and a memory device are integrated in a system LSI, in order to reduce the number of manufacturing steps and costs, these logic and memory device should be formed in the common manufacturing steps as long as possible. In a DRAM, data are stored in as capacitor in an electrical charge form. This capacitor has electrodes, called a cell plate electrode and a storage node electrode, on a semiconductor substrate region. The structure of this capacitor has a complicated shape, such as a hollow cylindrical shape, in order to reduce the occupancy area of the capacitor and to increase the capacitance thereof as far as possible. With a DRAM and logic mixed process for forming a DRAM and a logic in the same manufacturing steps, transistors of the logic and those of the DRAM are formed in the same manufacturing steps. However, it becomes necessary to carry out a manufacturing step for forming capacitors of the DRAM, and a flattening step for reducing a step height between the DRAM and the logic or between the memory array of the DRAM and the peripheral circuitry thereof, wherein the step height is caused based on the three-dimensional structure of the capacitors of the DRAM. Thus, problems that the number of manufacturing steps increases significantly and chip costs increases are caused.
In an SRAM, its memory cell is composed of 4 transistors and 2 load elements. These load elements are usually formed of MOS transistors (insulated gate field effect transistors), but are not formed of capacitors or the like. Therefore, the SRAM can be formed through a full CMOS logic process. That is, the SRAM and a logic can be formed in the same manufacturing steps. An SRAM has been used, for example, for a register file memory and a cache memory for a processor because of the high speed operability thereof and others.
In an SRAM, its memory cell is a flip-flop circuit. Thus, so far as a power supply voltage is supplied to the SRAM, data are held therein. Therefore, the SRAM does not require any refreshing for holding data, unlike a DRAM. Accordingly, the SRAM does not require any complicated memory control associated with the refreshing which is indispensable for the DRAM. For the SRAM, therefore, control is made simpler than for the DRAM. Thus, the SRAM is widely used as a main memory in order to simplify the system structure of a portable information terminal and such.
However, in portable information terminals, a larger quantity of data such as voice data and image data must be handled with a recent improvement in functions thereof. Thus, a memory having a large memory capacity is strongly required.
Concerning DRAM, the size thereof is being shrunk (is being miniaturized) as the miniaturizing process is being developed. For example, in a 0.18-&mgr;m DRAM process, a cell size of 0.3 square &mgr;m is achieved. On the other hand, in SRAMs, their full CMOS memory cell is composed of 2 P channel MOS transistors and 4 N channel MOS transistors, that is, 6 MOS transistors as a whole. Even if the shrinking process advances, it is necessary to isolate an N well for forming the P channel MOS transistors in a memory cell from a P well for forming the N channel MOS transistors thereof. Because of a restriction due to separation distance between the wells and others, the shrinking of the memory size in SRAMs advances less than in DRAM. For example, the memory size of an SRAM with a 0.18-&mgr;m CMOS logic process is about 7 square &mgr;m, and is about 20 times greater than the memory size of DRAM. Thus, when an SRAM is used as a main memory having a large memory capacity, the size of the chip becomes very large. Accordingly, it is very difficult to merge an SRAM having a memory capacity of 4 M bits or more with a logic in a system LSI having a restricted chip area.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device having a small occupancy area and making it possible to achieve a large memory capacity without increasing the number of manufacturing steps significantly.
Another object of the present invention is to provide a semiconductor memory device which has an array configuration of a small occupancy area and can be produced with a process similar to a CMOS process.
A further object of the present invention is to provide a semiconductor memory device having a memory cell configuration which has a small occupancy area and is suitable for a CMOS production process.
A still further object of the present invention is to provide a semiconductor memory device having a memory cell configuration which has a small occupancy area and is based on DRAM cells.
A semiconductor memory device according to a first aspect of the present invention includes memory cells arranged in row and columns and each including a capacitor having a cell plate electrode receiving a reference voltage and a storage electrode for accumulating electric charges according to storage data; and word lines arranged corresponding to the rows of memory cells and each connecting to the memory cell in the corresponding row. These word lines are formed in the same interconnecting layer as the cell plate electrodes.
The semiconductor memory device according to the first aspect of the present invention further includes bit lines arranged corresponding to the columns of memory cells, and each connecting to the memory cells in the corresponding column; and a row selecting circuit for selecting an addressed word line from the word lines in accordance with an address signal. The bit lines are arranged in pairs, and the memory cells are arranged such that data in the selected memory cells are simultaneously read out onto the bit lines in a pair by a selected word line.
A semiconductor memory device according to a second aspect of the present invention includes memory cells arranged in rows and columns. Each of the memory cells includes a capacitor having a cell plate electrode receiving a reference voltage and a storage electrode for accumulating electric charges according to storage data.
The semiconductor memory device according to the second aspect of the present invention further includes word l
Arimoto Kazutami
Shimano Hiroki
McDermott Will & Emery LLP
Renesas Technology Corp.
Yoha Connie C.
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