Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2002-10-17

2004-10-26

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S210000, C257S211000, C365S051000, C365S063000, C365S171000, C365S173000

Reexamination Certificate

active

06809366

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device. More particularly, the present invention relates to a non-volatile semiconductor memory device suitable for increased capacity and increased read and write operation speeds.
Recent progress in miniaturization technology raises a demand for a non-volatile semiconductor memory device having an increased capacity and increased read and write operation speeds.
An example of such a non-volatile semiconductor memory device is disclosed in Japanese Laid-Open Publication No. 6-77437. This non-volatile semiconductor memory device will now be described.
FIG. 7
is a circuit diagram showing a memory cell array of a conventional non-volatile semiconductor memory device.
As shown in
FIG. 7
, the memory cell array of the conventional non-volatile semiconductor memory device includes a plurality of word lines
102
, a plurality of bit lines
103
, source lines
104
, and a plurality of memory cells
101
. The plurality of word lines
102
are provided in the row direction. The plurality of bit lines
103
are provided in the column direction so as to cross the word lines
102
in a grade separation manner. Each of the source lines
104
is provided between corresponding two bit lines
103
so as to cross the word lines
102
in a grade separation manner. Each of the plurality of memory cells
101
is a transistor having a gate electrode
107
, a source region
106
, a drain region
105
and a floating gate
117
. Each gate electrode
107
is connected to a corresponding word line
102
, each drain region
105
is connected to a corresponding bit line
103
, and each source region
106
is connected to a corresponding source line
104
. In other words, the memory cell array of the conventional non-volatile semiconductor memory device is formed from a multiplicity of memory cells
101
arranged in a two-dimensional matrix. Note that the memory cells
101
herein refer to a plurality of memory cells arranged in a two-dimensional matrix.
FIG. 8
is a plan view showing the structure of the memory cell array of the conventional non-volatile semiconductor memory device.
As shown in
FIG. 8
, the drain region
105
of each memory cell
101
is connected to a corresponding bit line wiring
110
(corresponding to the bit line
103
of
FIG. 7
) via a corresponding drain contact
108
, and the source region
106
of each memory cell
101
is connected to a corresponding source line wiring
111
(corresponding to the source line
104
of
FIG. 7
) via a corresponding source contact
109
.
Hereinafter, the positional relation between wirings will be described.
FIGS. 9
to
11
are cross-sectional views of the memory cell array of the conventional non-volatile semiconductor memory device in FIG.
8
. More specifically,
FIG. 9
is a cross-sectional view taken along line IX—IX in FIG.
8
.
FIG. 10
is a cross-sectional view taken along line X—X in FIG. S.
FIG. 11
is a cross-sectional view taken along line XI—XI in FIG.
8
. Note that, for clarity, an interlayer insulating film which fills the gap between the bit line wiring
110
and the source line wiring is not shown in the figures.
As shown in
FIGS. 9
,
10
,
11
, each memory cell
1
has a substrate, a p-type well
112
provided on the substrate, an element isolation insulating film
113
provided on the p-type well
112
so as to surround a multiplicity of active regions, a tunnel insulating film
116
provided on the active regions of the substrate, a floating gate
117
provided on the tunnel insulating film
116
, an inter-gate-electrode insulating film
118
which covers the top and side surfaces of the floating gate for insulation, and a gate electrode
107
provided on the inter-gate-electrode insulating film
118
. Of the active regions, a highly-doped source region
106
and a highly-doped drain region
105
are provided in the p-type well
112
on both sides of the gate electrode
107
.
The memory cell array of the conventional non-volatile semiconductor memory device has at least one wiring layer on the interlayer insulating film (not shown in
FIGS. 9
to
11
) provided on the memory cells
101
. The bit line wirings
110
and the source line wirings
111
are provided in the same wiring layer at prescribed intervals. The bit line wiring
110
and the source line wirings
111
are arranged alternately. For illustration, individual bit line wirings
110
are herein referred to as bit line wirings D
1
, D
2
, D
3
, D
4
, individual source line wirings
111
are herein referred to as source line wirings S
1
, S
2
, S
3
, S
4
, and the memory cells having a common gate electrode G
1
are herein referred to as memory cells
101
a
,
101
b
,
101
c
,
101
d
from the left side of FIG.
8
. The bit line wiring D
1
is connected to the drain region of the memory cell
110
a
via a drain contact
108
a
which extends through the interlayer insulating film. Similarly, the bit line wirings D
2
, D
3
, D
4
are respectively connected to the drain regions of the memory cells
101
b
,
101
c
,
110
d
via drain contacts
108
b
,
108
c
,
108
d
. As shown in
FIG. 11
, the source line wirings S
1
, S
2
, S
3
, S
4
are respectively connected to the source regions of the memory cells
101
a
,
101
b
,
101
c
,
101
d
via source contacts
109
a
,
109
b
,
109
c
,
109
d.
This non-volatile semiconductor memory device is capable of writing and erasing information with relatively low power consumption by using a tunneling phenomenon.
Although further miniaturization is demanded for the non-volatile semiconductor memory devices in order to improve an integration degree, the conventional cell array structure as described above hinders such further miniaturization. In other words, in the memory cell array of the conventional non-volatile semiconductor memory device, two wirings formed in the same wiring layer are provided in a single memory cell width of the word line direction (row direction). This limits the memory cell width of the word line direction to the width that allows two wirings to be provided. Moreover, in the case where a plurality of wirings are formed in the same wiring layer, the wirings must be provided at prescribed intervals in view of the miniaturization limits. Therefore, the gap between the wirings cannot be reduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a non-volatile semiconductor memory device having a reduced area of the memory cell array as compared to the conventional examples while maintaining the same functions as those of the conventional examples.
A non-volatile semiconductor memory device of the present invention includes a plurality of non-volatile memory cells, a plurality of wiring layers, and a plurality of first wirings. Each of the plurality of non-volatile memory cells has a semiconductor substrate, a gate electrode, first and second impurity diffusion layers provided in the semiconductor substrate on both sides of the gate electrode, and an information storage section capable of holding information. The plurality of wiring layers are provided above the non-volatile memory cells at different levels. The plurality of first wirings are respectively connected to the first impurity diffusion layers and provided in a column direction so as to be electrically independent of each other. The first wirings have a plurality of partial wirings separately provided in the plurality of wiring layers. When viewed two-dimensionally, the partial wirings are separated from each other at a separation width smaller than a minimum separation width that is obtained when the partial wirings are provided in the same wiring layer.
The above structure enables reduction in density of the first wirings per wiring layer while maintaining the same functions as those of the conventional array structure. Accordingly, the area required for the wirings can be reduced as compared to the case where the first wirings are provided in the same wiring layer. As a result, the memory cell area can be reduced as

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