Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2002-11-07
2004-12-14
Hu, Shouxiang (Department: 2811)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S350000, C438S365000
Reexamination Certificate
active
06830982
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is in the field of fabrication of semiconductor devices. More specifically, the invention is in the field of fabrication of NPN transistors.
2. Related Art
In one type of bipolar transistor, and more particularly an NPN heterojunction bipolar transistor (“HBT”), used as an example in the present application, a thin silicon-germanium (“SiGe”) layer is grown as the base of the bipolar transistor on a silicon wafer. The NPN SiGe HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Speed and frequency response can be compared by the cutoff frequency which, simply stated, is the frequency where the gain of a transistor is considerably reduced. Cutoff frequencies in excess of 100 GHz have been achieved for the NPN SiGe HBT, which are comparable to the more expensive GaAs. Previously, silicon-only devices have not been competitive for use where very high speed and frequency response are required.
The higher gain, speed and frequency response of the NPN SiGe HBT are possible due to certain advantages of silicon-germanium, such as a narrower band gap and reduced resistivity. These advantages make silicon-germanium devices more competitive than silicon-only devices in areas of technology where high speed and high frequency response are required. The advantages of high speed and high frequency response discussed above require, among other things, an NPN SiGe HBT having a thin base layer with low base resistance.
By way of background, in a typical NPN SiGe HBT, a P-type base layer is formed by depositing a P-type doped SiGe film on a silicon substrate. A cap layer is formed over the P-type base layer and doped with a P-type dopant, such as boron. An emitter is then formed on the cap layer and doped with an N-type dopant, such as arsenic. The emitter also defines an intrinsic base region of the base layer situated directly below the emitter and extrinsic base regions situated on either side of the intrinsic base region. The intrinsic base region of the NPN SiGe HBT is connected to external components or devices via base contacts formed on the extrinsic base regions of the base layer. In an effort to improve device performance by increasing speed and frequency response, semiconductor manufacturers have, among other things, attempted to reduce overall base resistance of the NPN SiGe HBT by reducing the resistance of the extrinsic base regions.
In a conventional attempt to reduce the resistance of the extrinsic base regions of the NPN SiGe HBT, semiconductor manufacturers typically implant the extrinsic base regions with a high concentration of boron, which is a P-type dopant that is activated by heat in an anneal process. It is desirable to have a high concentration of boron near the top surface of the extrinsic base regions to reduce base resistance without adding to the undesirable base to collector capacitance. However, boron has an undesirable tendency to easily diffuse when subjected to heat in an anneal process. The extension, perpendicular to the surface of the wafer, of the dopant profile in the diffusion process undesirably increases the base to collector capacitance.
Semiconductor manufacturers have attempted to reduce the diffusion of boron in the extrinsic base regions of the NPN SiGe HBT by greatly reducing the thermal budget after deposition of the base layer of the NPN SiGe HBT. However, NPN SiGe HBTs are often fabricated with metal oxide semiconductor (“MOS”) transistors on the same substrate using Bipolar Complementary-Metal-Oxide-Semiconductor (“BiCMOS”) technology. In a typical BiCMOS process, the NPN SiGe HBT needs to withstand a CMOS thermal budget required to activate dopants in the MOS devices. The CMOS thermal budget, for example, can include a high temperature, e.g. between approximately 900.0° C. and approximately 1050.0° C., rapid anneal for approximately 5 to 30 seconds. Thus, a large reduction in the thermal budget to accommodate the NPN SiGe HBT can have an undesirable effect on formation of MOS devices in a BiCMOS process.
Thus, there is a need in the art for reducing the extrinsic base resistance in an NPN bipolar transistor, such as an NPN SiGe HBT, without requiring a lower thermal budget or decreasing manufacturability of the NPN bipolar transistor.
SUMMARY OF THE INVENTION
The present invention is directed to method for reducing extrinsic base resistance and improving manufacturability in an NPN transistor and related structure. The present invention addresses and resolves the need in the art for reducing the extrinsic base resistance in an NPN bipolar transistor, such as an NPN SiGe HBT, without requiring a lower thermal budget or decreasing manufacturability of the NPN bipolar transistor.
According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium.
According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon and may have a thickness less than 100.0 Angstroms. The indium dopant may extend to, for example, a depth of between approximately 10.0 Angstroms and approximately 100.0 Angstroms in the portion of the cap layer situated over the extrinsic base region.
According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon. In another embodiment, the present invention is a method that achieves the above-described NPN bipolar transistor. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
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Howard David
Racanelli Marco
U'Ren Greg D.
Farjami & Farjami LLP
Hu Shouxiang
Newport Fab LLC
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