Dual-L2 processor subsystem architecture for networking system

Details Dual-L2 processor subsystem architecture for networking system Dual-L2 processor subsystem architecture for networking system

2000-12-07

2004-06-15

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S123000, C711S130000, C711S153000, C711S173000

Reexamination Certificate

active

06751704

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to computer architectures and, more particularly, to a memory management scheme and architecture for allowing faster access to data and instructions.
2. Description of the Related Art
As computer and networking applications become Input/Output (I/O) intensive, the conventional computer architecture is becoming a limiting factor in obtaining higher processing speeds. Conventional computer architectures typically utilize a processor and memory architecture that creates a bottleneck in accessing data as memory accesses are slow and multiple devices and applications compete for memory access.
Conventional computer architectures generally utilize a cache comprising smaller, high-speed memory in addition to larger, slower main memory, such as Dynamic Random Access Memory (DRAM), in an attempt to increase memory access speeds. The cache typically stores a subset of shared data stored in main memory, which is generally paged in and out of the cache.
Cache is typically configured in multiple levels. Level 1 (L1) cache is usually designed into the processor chip and is commonly referred to as internal cache. Level 2 (L2) cache is the external memory closest to the processor chip. Additional levels are possible, but with each additional level, the access speed typically decreases.
In a microprocessor-based design, when the processor performs a read instruction, the processor first attempts to read the requested data from the cache. If the requested data is found in the cache, the slower main memory is not accessed. If the requested data is not contained in the cache, however, older data is paged out of the cache and the requested data is paged into the cache. The paging of data out of cache frequently requires additional memory delays and memory accesses because the data is frequently shared by other applications and/or devices, and the data must be re-read from the shared memory into the cache, resulting in slower memory access speeds.
The above description is particularly troublesome in networking environments involving the movement of packet data within a networking system. The movement of shared data can be broken down into 3 basic steps: (a) exchange of buffer information or Direct Memory Access (DMA) descriptors, (b) transfer of packet data to and from main memory, and (c) process of packet header by the processor. Steps (a) and (b) involve networking interface devices accessing shared data. Steps (a) and (c) involve the processor accessing the same blocks of shared data. Therefore, shared data are generally accessed by both the networking interface devices and the processor.
Conventional architectures utilizing an L2 cache, however, are designed to provide only the processor with access to the L2 cache. As a result, packet traffic cannot benefit from fast memory such as the L2 cache. Instead, packet buffers are transferred between the cache and the main memory store as they are accessed by the processor and the networking interface devices. In a conventional design, these actions will cause the shuffling of shared data back and forth between the L1/L2 caches and the main memory store.
Prior attempts to fix the limitations of the conventional computer architecture discussed above are not optimal for I/O intensive network router applications. Attempts utilizing DRAM technology are inefficient due to the limited memory bandwidth of the DRAM. Other attempts, such as employing a distributed routing scheme and/or specialized hardware with Static Random Access Memory (SRAM), are generally expensive and involve a redesign of the system.
Therefore, there is a need for a caching scheme to further extend the life of generic computing architecture in networking products to allow an efficient and cost-effective memory scheme.
SUMMARY OF THE INVENTION
The present invention comprises a method for providing an efficient and cost-effective memory caching scheme. This is achieved by configuring a computer memory architecture to utilize dual-L2 caches, preferably configured as an L2 Program Cache and an L2 Packet Cache. By use of this invention, memory access speeds may be increased as paging shared data is decreased and networking interface devices are given access to fast caches.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawing wherein like reference numbers represent like parts of the invention.


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