Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-10-30
2004-10-12
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06804809
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a system and method for generating a layout of a semiconductor device, and more particularly to a system and method to efficiently customize the layout for a semiconductor device based on existing layout information.
Semiconductor circuits or “chips” have become widely used in nearly all machines and products that have electronic components. A typical electronic circuit design is initially conceived and tested schematically by a circuit design engineer, with a number of components and devices connected together to yield a circuit with desired performance characteristics. Once the circuit has been designed, it must be reconfigured from schematic form into a layout form. This is typically a job for a physical design engineer, working in concert with the circuit design engineer to create a graphic layout specifying a suitable semiconductor implementation of the circuit. The graphic layout of the device, which specifies all of the semiconductor device layout parameters, is then submitted to a foundry for fabrication of the chip.
Laying out an electronic circuit in a semiconductor implementation is a complicated task, and is governed by a large number of geometric rules. A layout of a semiconductor device contains geometric features such as polygons to indicate proper size, shape, location and separation of a certain physical feature of the circuit (a sub-component within a semiconductor device) from other physical features, or to indicate proper isolation and separation among the circuit elements. The layout of a typical semiconductor device contains multiple drawing layers, each layer having one or more polygons. Generally, the more complicated the device is, the more layers and polygons the layout includes.
Furthermore, because an electronic circuit usually includes a number of components or devices, the layout of each device in an electronic circuit needs not only to include layers that indicate how the device itself is to be fabricated, but also layers that indicate how the device is connected with other devices on the same circuit or external devices, and how a conductive portion or element of the device is connected to other conductive portions or elements of the same device. The latter type of layers generally relate to metallization, which is the formation of electrical contacts to conductive elements in the semiconductor integrated circuit. Many devices further require formation of multilevel metal signal lines for a multilayer substrate on which the semiconductor devices are mounted. To do this, multilayer metallization and intermediate connecting layers, often called vias or via layers, are used to form a proper interconnection between the metallization layers. Through this multilayered structure, proper interconnections are made possible between both the conductive elements within the same device and those that are external. Such multilayer structure further complicates the layout process.
Drawing all of the layers separately and manually is tedious and error prone. In the past decades, efforts were dedicated to the development of layout automation methodologies. For example, basic device cell generators were developed to increase the productivity of layout design. Among the device cell generators, the most commonly used is a technique called parameterized cell, or pcell, developed by Cadence Design Systems, Inc., San Jose, Calif. A pcell is a programmable layout which allows users to specify their own parameters such as transistor size and finger number. It can be created either graphically or using SKILL™ code (SKILL is a trademark of Cadence, Inc.) Parameterized cells (pcells) are basically layout macros. A design engineer completes a pcell by filling in various parameters, and the layout of the pcell automatically changes to reflect these values. Pcells allow design layout at a higher level of abstraction. The pcell capability also allows the move from traditional “polygon pushing” to more automated design styles. Using pcells, a design engineer only needs to maintain a small set of design objects rather than all mask geometries. Because of these advantages, the use of pcells reduce design entry, editing time, and design rule violations.
Using device generators such as pcells, the layout of a single conventional device, such as a diode, a bipolar transistor, or a metal oxide semiconductor field-effect transistor (MOSFET), can be partially standardized in the layout for a certain manufacturing process and are programmed into a standard pcell for a parameterized layout generation. However, the degree of automation using a pcell depends on the degree of successful parameterization. With a transistor pcell, for example, the length, width, number of gate segments, and much more, can be realized by simply changing a parameter value. Furthermore, pieces of parameterized data can automatically appear, disappear, or replicate as a condition of another parameter. For bipolar designs, parameterized data can include arcs, circles, paths, and text. Although virtually any layout data for device designing customization can theoretically be realized using proper parameterization, doing so can be difficult or practically impossible in many situations. Particularly, in a device layout that requires multiple metallization layers, it is difficult or even impossible to incorporate all the necessary layers including the metallization and vias in a standard parameter cell (pcell), and parameterize all necessary layout customization for automatic layout generation. This will still leave a significant part of the layout process labor intensive.
One example of such customization that is difficult to parameterize is sizing. Sometimes a single device having a particular size is desired and this requires generating a layout of the device that has a specific size that is different from the size represented by an available pcell. Due to the intricacies of connectivity in a device having multiple layers, particularly multiple metallization and vias, the size of the layout cannot by realized by changing one or a few layer parameters. As a result, the satisfaction of a sizing requirement is much more complicated than just simply scaling up or down an available starting layout such as a standard pcell.
For example, a very low on-resistance is often required of an input or output drive such as an LDMOSFET (laterally diffused metal oxide semiconductor field-effect transistor). In order to achieve a very low on-resistance, the LDMOSFET needs to be very large. The complete layout of an LDMOSFET may comprise many layers including a gate polysilicon layer (POL), a contact layer (CON) for contact from metal-1 to polysilicon, a metal-1 layer (MT1) for innermost metallization, a via-1 layer (VIA1) for via connecting metal-1 to metal-2, a metal-2 layer (MT2) for second metallization, a via-2 layer (VIA2) via connecting metal-2 to top metal, a top metal layer (MTT) for uppermost metal, and a passivation layer (PSV). Among the necessary layers, the POL, CON, and PSV can be relatively easily incorporated and programmed into a pcell. However, the metallization layers are quite difficult to incorporate into the pcell due to the complexity in patterns and interconnectivities required of them. Although it is possible to construct the complete LDMOSFET driver of a desirable size by starting with a pcell containing all layers except metal layers, sizing the pcell, and then separately manually generating all metal and via layers and then placing them on top of the pcell, the process is time consuming, prone to error and relatively ineffective in optimizing metallization for low on-resistance.
It would therefore be an improvement in the art to provide a system and a method for laying out a semiconductor device that reduces the complexity for physical design engineers in creating layouts for a device of customizable features based on standard layout cells or blocks. Such a system and a method is the subject of the present invention.
BRIEF SUMMARY OF THE INVENT
Harlan Ronald
Kosier Steven L.
West Peter
Kinney & Lange , P.A.
Levin Naum
PolarFab LLC
Siek Vuthe
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