Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2003-04-02
2004-11-16
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S072000, C438S164000
Reexamination Certificate
active
06818922
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91134042, filed Nov. 22, 2002.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a thin film transistor array and driving circuit structure. More particularly, the present invention relates to a thin film transistor array and driving circuit structure that can be fabricated in six masking steps.
2. Description of Related Art
In recent years, the rapid advance in the fabrication of semiconductor devices and display devices has lead to the popularization of multimedia systems. Due to the production of high-quality and low-cost displays such as cathode ray tubes, these displays now represent a large chunk in the display market. However, from the standpoint of a desktop display user or an environmentalist, a cathode ray tube is bulky, consumes a lot of energy and is also a source of radiation. Since a lot of material is required to fabricate each cathode ray tube and a lot of energy is wasted in its operation, other types of displays including thin film transistor liquid crystal display (TFT-LCD) have been developed as a substitute. A conventional TFT-LCD is a slim and compact display capable of producing high-quality images. Each TFT-LCD uses very little energy and is virtually radiation-free. All these advantages have championed the TFT-LCD in the mainstream display market.
In general, a thin film transistor may be classified as an amorphous thin film transistor or a polysilicon thin film transistor. A polysilicon thin film transistor fabricated using a low-temperature polysilicon (LTPS) technique is different from an amorphous thin film transistor using an amorphous silicon (a-Si) technique. The LTPS transistor has an electron mobility greater than 200 cm
2
/V-sec and hence the thin film transistor can have a smaller dimension, a larger aperture ratio and a lower power rating. In addition, the LTPS process also permits the concurrent fabrication of a portion of the driving circuit and the thin film transistor in the same substrate so that the subsequently formed liquid crystal display panel has a greater reliability and a lower average production cost.
FIGS. 1A
to
1
H are schematic cross-sectional views showing the progression of steps for fabricating a conventional thin film transistor array and driving circuit. As shown in
FIG. 1A
, a substrate
100
is provided. A polysilicon layer is formed over the substrate
100
. Thereafter, the polysilicon layer is patterned using a first masking process (Mask
1
) so that a plurality of poly-islands
102
a
,
102
b
and
102
c
are formed over the substrate
100
. The poly-island
102
a
is a location for forming a thin film transistor while the poly-islands
102
b
and
102
c
are locations for forming a driving circuit such as a complementary metal-oxide-semiconductor (CMOS) circuit. Since the poly-island
102
a
is eventually transformed into a thin film transistor, poly-islands
102
a
are normally positioned on top of the substrate
100
as an array. Similarly, since the poly-islands
102
b
and
102
c
are eventually transformed into driving circuits, the poly-islands
102
b
and
102
c
are normally positioned close to the peripheral region of the substrate
100
.
As shown in
FIG. 1B
, a first dielectric layer
104
and a conductive layer (not shown) are sequentially formed over the substrate
100
with the poly-islands
102
a
,
102
b
and
102
c
thereon. The conductive layer is patterned using a second masking process (Mask
2
) to form gates
106
a
,
106
b
and
106
c
over the poly-islands
102
a
,
102
b
and
102
c
respectively and the lower electrode
108
of a storage capacity on a suitable location on the substrate
100
.
As shown in
FIG. 1C
, N+ doped regions
110
and N+ doped regions
112
are patterned out inside the island
102
a
and the island
102
c
using a third masking process (Mask
3
). The N+ doped regions
110
inside the island
102
a
is located on each side of the gate
106
a
and the N+ doped regions
112
inside the island
102
c
are located on each side of the gate
106
c.
As shown in
FIG. 1D
, N− doped regions
114
are patterned inside the island
102
a
and N− doped regions
116
are patterned inside the island
102
c
using a fourth masking process (Mask
4
). Each N− doped region
114
inside the island
102
a
is located between the gate
106
a
and one N+ doped region
110
. Similarly, each N− doped region
116
inside the island
102
c
is located between the gate
106
c
and one N+ doped region
112
.
As shown in
FIG. 1E
, P+ doped regions
118
are patterned inside the island
102
b
using a fifth masking process (Mask
5
). The P+ doped regions
118
inside the island
102
b
are located on each side of the gate
106
b.
As shown in
FIG. 1F
, a second dielectric layer
120
is formed over the substrate
100
. Thereafter, the first dielectric layer
104
and the second dielectric layer
120
are patterned using a sixth masking process (Mask
6
) to form openings
122
a
,
122
b
and
122
c
. The opening
122
a
exposes the N+ doped region
110
, the opening
122
b
exposes the P+ doped region
118
and the opening
122
c
exposes the N+ doped region
112
.
As shown in
FIG. 1G
, a conductive layer (not shown) is formed over the second dielectric layer
120
. Thereafter, the conductive layer is patterned using a seventh masking process (Mask
7
) to form source/drain terminals
124
(comprising
124
a
,
124
b
and
124
c
respectively). The source/drain terminals
124
are electrically connected to the N+ doped region
110
, the P+ doped region
118
and the N+ doped region
112
through the opening
122
a
, the opening
122
b
and the opening
122
c
respectively.
As shown in
FIG. 1H
, a planarization layer
126
is formed over the substrate
100
with the source/drain terminals
124
thereon. Thereafter, the planarization layer
126
is patterned using an eighth masking process (Mask
8
) to form an opening
128
for exposing the source/drain terminal
124
a
. After patterning the planarization layer
126
, a conductive layer (not shown) is formed over the substrate
100
. The conductive layer is a transparent layer typically made from indium-tin-oxide material. The conductive layer is patterned using a ninth masking process (Mask
9
) to form a pixel electrode
130
.
As shown on the left side of
FIG. 1H
, the N− doped region
116
and the N+ doped region
112
inside the island
102
c
, the gate
106
c
and the source/drain terminal
124
c
together constitute an N-type metal-oxide-semiconductor (NMOS) transistor. The P+ doped region
18
inside the island
102
b
, the gate
106
b
and the source/drain terminal
124
b
together constitute a P-type metal-oxide-semiconductor (PMOS) transistor. The NMOS transistor and the PMOS transistor together constitute a complementary metal-oxide-semiconductor (CMOS) transistor. The CMOS transistor on the substrate
100
is a driving circuit for driving the thin film transistor on the right side of FIG.
1
H and hence controlling the pixel display.
As shown on the right side of
FIG. 1H
, the N− doped region
110
and the N+ doped region
114
inside the island
102
a
, the gate
106
a
and the source/drain terminal
124
a
together constitute a polysilicon thin film transistor (poly-TFT). The writing of data into the pixel electrode
120
of the thin film transistor is driven and controlled by the CMOS.
FIG. 2
is a flow chart showing the steps for fabricating a conventional thin film transistor array and driving circuit. As shown in
FIG. 2
, the process of fabricating the thin film transistor array and the driving circuit includes: patterning a polysilicon layer (S
200
); patterning out a gate and the lower electrode of a storage capacitor (S
202
); patterning out a N+ doped region (S
204
), patterning out an N− doped region (S
206
); patterning out a P+
Jr. Carl Whitehead
Liu & Liu
Smoot Stephen W.
Toppoly Optoelectronics Corp.
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