Apparatus for selectively providing RAS signals or RAS timing an

Details Apparatus for selectively providing RAS signals or RAS timing an Apparatus for selectively providing RAS signals or RAS timing an

1989-11-13

1991-04-02

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Signals

36523002, 36523006, 36523008, 365233, 36518903, 365222, G11C 700, G11C 11408

Patent

active

050051571

ABSTRACT:
An improved memory controller which can support varying numbers of banks of memory without requiring any more RAS output pins than are necessary for a minimum number of banks of memory. The memory controller chip has N RAS output pins. An internal decoder selects one of N decode outputs after decoding internally provided coded RAS addresses. A timing signal is generated to control the duration of the selected decoder output to provide the proper pulse length for the RAS signal. An internal multiplexer, with its outputs coupled to the RAS output pins, selects either the N decode outputs from the decoder or the timing signal and the internally provided addresses directly.

REFERENCES:
patent: 4564926 (1986-01-01), Nikaido et al.
patent: 4797850 (1989-01-01), Amitai
patent: 4809234 (1989-02-01), Kuwashiro
patent: 4881206 (1989-11-01), Kadono

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