Method of pull back for forming shallow trench isolation

Details Method of pull back for forming shallow trench isolation Method of pull back for forming shallow trench isolation

2003-08-08

2004-12-07

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S729000, C438S424000

Reexamination Certificate

active

06828248

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabrication of a semiconductor integrated circuit. More particularly, the present invention relates to a method for forming a shallow trench isolation (STI) structure.
2. Description of the Related Art
Because of the high level integration of semiconductor integrated circuits, a variety of isolation techniques are proposed and used to provide electrical isolation between devices fabricated within the integrated circuits. Traditionally, local oxidation of silicon (LOCOS) is used to isolate the devices of integrated circuits fabricated within 0.35 micron (um) or 0.25 um semiconductor technology. Usually, LOCOS is formed by a thermal oxidation process. Because of the thermal oxidation process, Bird's Beak effects occur after LOCOS structures are formed. To eliminate or avoid the effects, larger spaces to separate the devices of integrated circuits are required.
However, higher level of integration of circuits is the trend in semiconductor fabrication. To avoid Bird's Beak effects and reduce the size of integrated circuits, shallow trench isolation (STI) has been gradually replacing the conventional semiconductor device isolating method, LOCOS, in quarter micron or deep submicron technology. Conventionally, a STI process uses a thick nitride layer as a hard mask. After a trench is formed within the silicon substrate and the nitride layer, an oxide layer is used to fill the trench. Then this nitride layer or hard mask performs as a chemical-mechanical polish (CMP) stop layer for removal of the oxide layer.
However, some problems still exist in STI. The interface of vertical sidewalls of the trench and the top surface of semiconductor substrate produces sharp corners. As a result, a gate dielectric layer subsequently deposited suffers from stress at the sharp corner regions. In addition, the electric field at sharp corners contributes to parasitic subthreshold leakage and degrades gate oxide integrity. Therefore, new methods and structures are provided to avoid the issues.
A method to eliminate the sharp corner issue by a pull-back process is provided in U.S. Pat. No. 6,265,317 called U.S. '317 hereafter.
FIG. 1
is a schematic cross-sectional diagram illustrating a structure formed by the method disclosed in U.S. '317. A pad oxide layer
110
and a pad nitride layer
120
are sequentially formed upon a silicon substrate
100
. A patterned photoresist layer is used to form a trench
130
within the silicon substrate
100
, the pad oxide layer
110
and the pad nitride layer
120
. After the removal of the photoresist layer, the pad nitride layer
120
is then briefly and selectively etched by phosphoric acid (H
3
PO
4
) solution and pulled back from the trench rim and exposes a small amount of the underlying pad oxide
110
. Then a sputtering process is perfomed to round corners
140
. However, the method still has some problems, such as overhang and the control of the H
3
PO
4
wet-etching process.
Another top corner rounding method is disclosed in U.S. Pat. No. 6,391,729. Referring to
FIG. 2
, a pad oxide layer
210
and a pad nitride layer
220
are sequentially formed upon a silicon substrate
200
. A patterned photoresist layer is used to form a trench
230
within the silicon substrate
200
, the pad oxide layer
210
and the pad nitride layer
220
. After removal of the photoresist layer, a sputtering technique is performed to substantially trim the entire pad nitride layer
220
, and the pad oxide layer
210
, while rounding the trench corners
240
. However, because the entire pad nitride layer
220
is trimmed and damaged, it is difficult to control a subsequent chemical-mechanical polish (CMP) process used to remove a high density plasma (HDP) oxide layer. Moreover, the CMP process can result in non-uniformities of the substrate surface and cause deviations of critical condition (CD) in a following photographic process for gate patterns.
Accordingly, it is desirable to provide a method for forming a shallow trench isolation without the problems aforementioned.
SUMMARY OF THE INVENTION
A method of forming a shallow trench isolation (STI) structure includes providing a substrate having a hard mask layer disposed thereupon, and a dielectric layer above the hard mask layer. Then a trench is formed within the hard mask layer, the dielectric layer and the substrate. Finally, the hard mask layer and the dielectric layer are pulled back by a dry etching process using a halogen containing etching gas.


REFERENCES:
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patent: 5998852 (1999-12-01), Berry et al.
patent: 6156629 (2000-12-01), Tao et al.
patent: 6265317 (2001-07-01), Chiu et al.
patent: 6391729 (2002-05-01), Hui
patent: 6524964 (2003-02-01), Yu
patent: 2003/0155329 (2003-08-01), Su et al.
patent: 2003/0181048 (2003-09-01), Huang et al.

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