Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2001-06-15
2004-08-31
Lee, Eddie (Department: 2811)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S345000, C438S327000, C438S343000, C438S325000, C438S364000, C438S236000, C438S204000, C438S207000
Reexamination Certificate
active
06784065
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bipolar transistor and, more particularly, to a bipolar transistor with an ultra-small, self-aligned polysilicon emitter and a method of forming the transistor.
2. Description of the Related Art
A bipolar transistor is a three-terminal device that can, when properly biased, controllably vary the magnitude of the current that flows between two of the terminals. The three terminals include a base terminal, a collector terminal, and an emitter terminal. The charge carriers, which form the current, flow between the collector and the emitter terminals, while variations in the voltage on the base terminal cause the magnitude of the current to vary.
Due to the increasing demand for battery-powered devices, there is a need for a bipolar transistor that utilizes less power. Lower power consumption can be obtained by reducing the maximum current that can flow between the two terminals. One approach for reducing the maximum current is to reduce the size of the base-to-emitter junction, preferably to sub-lithographic feature sizes.
FIG. 1
shows a cross-sectional diagram that illustrates a portion of a prior-art bipolar transistor
100
that has a base-to-emitter junction with a sub-lithographic width. As shown in
FIG. 1
, transistor
100
includes a collector layer
110
, a base layer
112
that is formed on collector layer
110
, and a field oxide region FOX that adjoins layer
112
. In addition, transistor
100
includes a thin oxide layer
114
that is formed on a portion of base layer
112
and the field oxide region FOX, and an n+ extrinsic emitter
116
that is formed on thin oxide layer
114
.
As further shown in
FIG. 1
, transistor
100
also includes an n+ intrinsic emitter region
118
that is formed in base layer
112
, and an n+ poly ridge
120
that is connected to extrinsic emitter
116
and n+ intrinsic emitter region
118
. Extrinsic emitter
116
, intrinsic emitter region
118
, and poly ridge
120
form the emitter of transistor
100
.
Transistor
100
additionally includes a base silicide contact
122
that is formed on base layer
112
, and an emitter silicide contact
124
that is formed on extrinsic emitter
116
. In addition, an oxide spacer
126
is formed on base layer
112
between poly ridge
120
and base contact
122
.
During fabrication, poly ridge
120
is formed to have a maximum width (measured laterally) that is smaller than the minimum feature size that is obtainable with a given photolithographic process. After poly ridge
120
has been formed, emitter region
118
is formed during an annealing step which causes dopants to outdiffuse from poly ridge
120
into base layer
112
.
As a result, a very small base-to-emitter junction results. A small base-to-emitter junction limits the magnitude of the current that can flow through transistor
100
. Reduced current, in turn, provides lowpower operation. (See “Poly Emitter Transistor (PRET): Simple Low Power Option to a Bipolar Process,” Wim van der Wel, et al., IEDM 93-453, 1993, pp. 17.6.1-17.6.4.)
One drawback of transistor
100
, however, is that transistor
100
requires the added cost and complexity of a double polysilicon process (extrinsic emitter
116
is formed from a first polysilicon (poly-
1
) layer, while poly ridge
120
is formed from a second polysilicon (poly-
2
) layer). In addition, emitter dopant diffusion into base
112
can be less, compared to a conventional single-poly device architecture, due to the possible presence of oxide at the poly
1
-to-poly
2
interface (emitter
116
to poly ridge
120
interface).
Another drawback of transistor
100
is that, although
FIG. 1
shows oxide spacer
126
formed on poly ridge
120
, in actual practice it is difficult to form an oxide side-wall spacer on a sloped surface. Gaps can result which, in turn, can lead to an electrical short circuit between base layer
112
and extrinsic emitter
116
following the salicidiation process (the process that forms base silicide contact
122
and emitter silicide contact
124
). Silicide is not formed on oxide. Thus it is critical that a uniformly thick layer of oxide (spacer
126
) separate base layer
112
from extrinsic emitter
116
.
A further drawback of transistor
100
is that the slope of the end wall of extrinsic emitter
116
can effect the width of poly ridge
120
. Although
FIG. 1
shows extrinsic emitter
116
with a vertical end wall, in actual practice, the end wall is often non-vertical, and non-uniform across a wafer that has a number of bipolar transistors. This, in turn, can result in the bipolar transistors having varying performances.
An additional drawback of transistor
100
is that poly ridge
120
is formed around and in contact with each side wall of extrinsic emitter
116
. A plan view of extrinsic emitter
116
would show emitter
116
with a square or rectangular shape with poly ridge
120
surrounding emitter
116
. As a result, transistor
100
has a large base-to-emitter contact area and a high base-to-emitter capacitance.
Thus, there is a need for a low-power bipolar transistor with a sub-lithographic base-to-emitter junction that reduces, or preferably eliminates, the previously-described drawbacks.
SUMMARY OF THE INVENTION
The present invention provides a bipolar transistor that is formed with a single polysilicon process, and has a substantially vertical end wall. The vertical end wall allows a standard oxide side-wall spacer to be formed adjacent to the extrinsic emitter, thereby reducing the likelihood of any base-to-emitter short circuits.
In addition, the present invention forms a sub-lithographic emitter region that reduces the maximum current that can flow through the transistor, thereby reducing power consumption. The present invention also reduces the base-to-emitter capacitance by limiting the base-to-emitter contact area.
The bipolar transistor of the present invention is formed on a wafer that has a buried layer, an epitaxial layer of a first conductivity type that is formed over the buried layer, and an intrinsic base region of a second conductivity type that is formed in the epitaxial layer. The epitaxial layer has a smaller dopant concentration than the buried layer.
The bipolar transistor has an isolation region that formed on the surface of the intrinsic base region. The isolation region has a side wall. The transistor also has an extrinsic emitter region that is formed on the isolation region and the intrinsic base region. The extrinsic emitter region has a side wall. In accordance with the present invention, the side wall of the extrinsic emitter region is substantially aligned with the side wall of the isolation region. In addition, the region of the extrinsic emitter that contacts the intrinsic base has a sub-lithographic feature size.
The bipolar transistor further has an intrinsic emitter region that is formed in the intrinsic base region. The intrinsic emitter region contacts the extrinsic emitter region. The transistor additionally has an isolation spacer that is formed on the intrinsic base region to contact the extrinsic emitter.
The present invention also includes a method for forming a low-power bipolar transistor. The bipolar transistor is formed on a wafer that has a buried layer, an epitaxial layer of a first conductivity type that is formed over the buried layer, and an intrinsic base region of a second conductivity type that is formed in the epitaxial layer. The epitaxial layer has a smaller dopant concentration than the buried layer.
The method of the present invention begins by forming an isolation region on the intrinsic base region. The method includes the steps of forming a layer of conductive material on the isolation region and the intrinsic base region, and etching the layer of conductive material to form an extrinsic emitter on the isolation region and the intrinsic base region.
The method further includes the step of etching the isolation region such that a side wall of the extrinsic emitter and a side wall of the isol
Lee Eddie
Magee Thomas
National Semiconductor Corporation
Pickering Mark C.
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