Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-11
2004-08-03
Kielin, Erik J. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S657000
Reexamination Certificate
active
06770555
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a process for fabricating a semiconductor integrated circuit device and, more particularly, to a process for fabricating a semiconductor device having contact holes to a polycide signal line and an impurity region.
DESCRIPTION OF THE RELATED ART
The integration density of semiconductor integrated circuit has been increased through a scaling down of circuit components/signal lines. The signal lines of a semiconductor integrated circuit device are getting narrow. The narrow signal line increases the resistance against an electric signal, and the large-resistance signal line retards the signal propagation. In order to decrease the resistance, a polycide structure has been proposed for the signal line. The polycide structure is a lamination of a polysilicon layer and a refractory metal silicide. A multi-layered wiring structure is employed in the semiconductor integrated circuit device, and upper-level signal lines are connected to lower-level signal lines through contact holes. The contact holes are also miniaturized in the semiconductor integrated circuit device. If conductive metal is deposited over an inter-level insulating layer having miniature contact holes by using a sputtering technique, the step-coverage is poor, and the conductive metal does not fill the miniature contact holes. If the conductive metal layer is patterned into an upper-level signal line, the contact resistance between the upper-level signal line and a lower-level signal line is large or unstable between products. For this reason, it is not desirable to deposit the conductive metal over the inter-level signal line through the sputtering.
Polysilicon is usually deposited through a chemical vapor deposition, and the step coverage is improved. For this reason, it is appropriate to form the upper-level signal layer of polysilicon or the upper-level signal line with the polycide structure. When a manufacturer connects an upper-level polycide line through a miniature contact hole to a lower-level polycide line, the manufacturer encounters a problem in large contact resistance between the polysilicon layer of the upper-level polycide line and the refractory metal silicide layer of the lower-level polycide line.
A solution is proposed in Japanese Patent Publication of Unexamined Application No. 60-15950. According to the solution disclosed in the Japanese Patent Publication of Unexamined Application, the refractory metal silicide layer is partially removed from the lower-level polycide line, and the polysilicon layer of the upper-level polycide layer is directly connected through a contact hole to the exposed polysilicon layer of the lower-level polycide line. The direct contact between the polysilicon layers decreases the contact resistance.
When a manufacturer forms the direct contact between the polysilicon layers in a semiconductor dynamic random access memory device, the direct contact is realized through a process shown in
FIGS. 1A
to
1
C.
The prior art process starts with preparation of a silicon substrate
1
, and a field oxide layer
2
is selectively grown on the major surface of the silicon substrate
1
. The field oxide layer
2
defines an active area in the major surface, and the active area is oxidized so that a gate oxide layer
3
is grown.
Polysilicon is deposited over the entire surface of the resultant structure, and refractory metal silicide is laminated on the polysilicon layer. The refractory metal silicide layer is produced through an alloying technique between the polysilicon layer and a refractory metal layer. Word lines
4
a
/
4
b
are expected to be low in resistance, and the polysilicon layer and the refractory metal silicide layer are thick. In this instance, the polysilicon layer is 1000 angstroms thick, and the refractory metal silicide layer is also 1000 angstroms thick. A photo-resist etching mask is formed on the refractory metal silicide layer by using photo-lithographic techniques, and the lamination is patterned into word lines
4
a
/
4
b
. The word lines
4
a
/
4
b
have the polycide structure, and a part of the word line
4
a
serves as a gate electrode on the gate oxide layer
3
.
Subsequently, n-type dopant impurity is ion implanted into the active area, and forms n-type source/drain regions
5
a
/
5
b
on both side of the channel region under the gate oxide layer
3
. Insulating material is deposited over the entire surface of the resultant semiconductor structure, and forms an interlevel insulating layer
6
. A photo-resist etching mask
7
is formed on the interlevel insulating layer
6
by using the lithographic techniques, and has openings over the word line
4
b
and the n-type drain region
5
a
. Using the photo-resist etching mask, the inter-level insulating layer
6
is selectively etched through a reactive ion etching technique. The reactive ion etching is continued for a time long enough to reach the surface of the n-type drain region
5
a
, because the n-type drain region
5
a
is deeper than the word line
4
b
. The time for the reactive ion etching is, by way of example, seventy seconds. Contact holes
8
a
/
8
b
are formed in the inter-level insulating layer
6
, and the word line
4
b
and the n-type drain region
5
a
are exposed to the contact holes
8
a
and
8
b
, respectively, as shown in FIG.
1
A. Although the reactive ion etching is continued after reaching the refractory metal silicide layer of the word line
4
b
, the refractory metal silicide layer is resistive against the etchant, and the contact holes
8
a
/
8
b
different in depth are concurrently formed in the interlevel insulating layer
6
.
Subsequently, the resultant semiconductor structure is subjected to a dry etching or a plasma etching, and the refractory metal silicide layer of the word line
4
b
is partially etched away. As a result, the polysilicon layer of the word line
4
b
is exposed to the contact hole
8
a
as shown in FIG.
1
B. The photo-resist etching mask
7
is stripped off.
Polysilicon is deposited over the entire surface of the semiconductor structure, and the polysilicon layer is held in contact with the polysilicon layer of the word line
4
b
and the n-type drain region
5
a
in the contact holes
8
a
/
8
b
. Subsequently, refractory metal is deposited over the polysilicon layer. The refractory metal is converted to refractory metal silicide, and the refractory metal silicide layer is laminated on the polysilicon layer. A photo-resist etching mask (not shown) is formed on the refractory metal silicide layer, and the refractory metal layer and the polysilicon layer are selectively etched away. Upper-level signal lines
9
a
and
9
b
are formed on the inter-level insulating layer
6
, and have the polycide structure as shown in FIG.
1
C.
The polysilicon layers of the upper-level signal lines
9
a
/
9
b
are directly held in contact with the polysilicon layer of the word line
4
b
and the n-type drain region
5
a
of the single crystal silicon. For this reason, low contact resistance is achieved through the prior art fabrication process. However, the manufacturer encounters a problem in that leakage current flows between the upper-level signal line
9
b
and the silicon substrate
1
.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a fabrication process through which contact holes different in depth are concurrently formed without increase of contact resistance and the serious leakage current.
The present inventor contemplated the problem inherent in the prior art structure, and noticed that the drain region had been depressed as shown in FIG.
2
. The present inventor thought that the etchant had removed the surface portion of the drain region
5
a
during the dry etching for the refractory metal silicide. As described hereinbefore, the word lines
4
a
/
4
b
had the refractory metal silicide layer of the order of 1000 angstroms thick, and the dry etching was continued for the long time. Even though the manufacturer used the dry etchant large in selectivity, the d
Kielin Erik J.
NEC Corporation
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