Memory cell with a capacitive structure as a control gate...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S315000, C257S316000, C257S357000, C257S369000, C438S257000, C438S396000, C438S688000, C438S689000, C438S526000, C438S745000

Reexamination Certificate

active

06806529

ABSTRACT:

FIG. 1
is a cross-sectional view illustrating an example of a memory cell
100
in accordance with the present invention.
FIGS. 2A-2C
are cross-sectional views illustrating an example of a method of forming a memory cell in accordance with the present invention.
FIGS. 3A-3B
are views illustrating an example of a memory cell
300
in accordance with the present invention.
FIGS. 4A-4C
are cross-sectional views illustrating an example of a method of forming a memory cell in accordance with the present invention.
FIGS. 5A and 5B
are views illustrating an example of a memory cell
500
in accordance with the present invention.
FIG. 5C
is a cross-sectional view illustrating an example of a memory cell
600
in accordance with the present invention.
FIGS. 6A-6F
are cross-sectional views illustrating an example of a method of forming a memory cell in accordance with the present invention.
FIGS. 7A-7C
are views illustrating an example of a memory cell
700
in accordance with the present invention.
FIGS. 8A-8F
are cross-sectional views taken along line
7
C-
7
C of
FIG. 7A
illustrating an example of a method of forming a memory cell in accordance with the present invention.


REFERENCES:
patent: 5761126 (1998-06-01), Chi et al.
patent: 6528842 (2003-03-01), Luich et al.
Dae M. Kim et al., “Stacked Gate Mid-Channel Injection Flash EEPROM Cell-Part 1: Programming Speed and Efficiency Versus Device Structure”, IEEE Transactions on Electron Devices, vol. 45, No. 8, Aug. 1998, pps. 1696-1702.

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