CMP in-situ conditioning with pad and retaining ring clean

Details CMP in-situ conditioning with pad and retaining ring clean CMP in-situ conditioning with pad and retaining ring clean

2003-01-15

2004-10-19

Wilczewski, M. (Department: 2822)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S693000, C451S041000, C451S056000, C216S088000, C216S089000

Reexamination Certificate

active

06806193

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to a method for reducing particulate defects on the surface of semiconductor wafers during the fabrication process. In particular, the invention relates to a method for reducing particle defects introduced during the chemical mechanical polishing or planarization (CMP) operation in the wafer fabrication process. More specifically, the invention relates to a method for preconditioning the CMP polishing pad and retaining ring with a cleaning chemistry for the purposes of particle and defect reduction.
BACKGROUND OF THE INVENTION
Modern-day semiconductor devices, commonly called microchips or integrated circuits, are fabricated in “cleanroom” environments using a multi-step process that constructs numerous integrated circuits in the form of chips, or “die,” on disc-shaped wafers. Due to the miniscule scale of circuitry on each integrated circuit, it is critical to the fabrication process that the wafers remain as clean and particle-free as possible, as even tiny particles may lead to defects that render a device inoperable, consequently lowering yield and associated profits. Critical to improving yield is raising the number of good die per wafer. To accomplish this, the semiconductor industry is moving in the direction of larger-diameter wafers and smaller die, so that more integrated circuits can be “squeezed” onto a single wafer. Also, more effective and efficient methods are sought for reducing particulate contamination of the wafers during the fabrication process.
Since the late 1950s, integrated circuit technology has evolved rapidly and has revolutionized virtually every industry and capacity in which integrated circuits are used. Today's integrated circuits frequently employ hundreds of thousands or even millions of transistors and highly complex, multi-layered designs. The proliferation of electronics in general, and integrated circuits in particular, has resulted in large part from the ability to increase circuit functionality while simultaneously reducing device cost and size. An important catalyst for these improvements has been advances in semiconductor processing technologies, the various techniques used to construct circuit elements—e.g., transistors, resistors and capacitors—on the semiconductor substrate, as well as the necessary conducting interconnects between individual circuit elements. Improved materials, equipment and processes have allowed increasingly complex circuits with improved speed, reduced power requirements and smaller footprints.
Integrated circuits are typically constructed at the surface of a silicon wafer sliced from a single-crystal ingot, although other semiconductors such as gallium arsenide and germanium are also used. Individual circuit elements are fabricated on the wafer surface. The electrical conduction between appropriate circuit elements, and electrical isolation between other circuit elements, is then established using alternating layers of appropriately patterned conductors and insulators. The circuit elements and their interconnections are formed using a series of processing steps including ion implantation, thin film deposition, photolithography, selective etching, as well as various cleaning processes.
As die sizes shrink with newer technology, the functionality of integrated circuits is increasing, as are the number of active metal layers on each die. Integrated circuits are fabricated in layers using several complex operations, with many processes repeated as each layer is created. An inlaid or damascene interconnect scheme is typically used for forming copper metallization, wherein an insulating dielectric layer is deposited, followed by the formation of trenches and vias through patterning and etching processes. A diffusion barrier and copper seed layer are then deposited, followed by electrochemical plating of the copper to fill the trenches and vias. A chemical mechanical planarization (CMP) process is then used to remove the excessive portion of the copper and to planarize the surface of the wafer.
The slurries used in CMP are best classified by the types of layers, or films, they are intended to planarize. In semiconductor manufacturing, CMP processes are most commonly used for films comprised of silicon oxide, tungsten, copper, tantalum and titanium. CMP of copper films, for example, often employs slurries based on ammonia, which offers high copper ion solubility through ion complexation.
In addition to polishing of metallization layers, CMP processing generally also involves barrier layer and dielectric layer polishing. A barrier layer is a layer disposed between two layers that prevent one layer from contaminating the other layer and vice versa. Copper metallization schemes often employ barrier metals such as tantalum or tantalum-rich alloys between the copper and dielectric layers to minimize cross-contamination between those layers. Dielectric layers provide electrical isolation between conducting layers, and are frequently comprised of an oxide material such as silica. An integrated CMP processing technique should allow the polishing and planarization of alternating layers such as those described—e.g., a layer comprising copper on a layer comprising tantalum on a layer comprising oxide.
Photolithography involves spinning a light-sensitive photoresist material onto the wafer surface. Next, using precise optical processes, individual integrated circuits are formed by repetitively exposing a pattern on a glass mask, or reticle, in a grid-like fashion onto the photoresist material. The exposed photoresist material is typically cured and developed, then dissolved areas of the photoresist are rinsed away, leaving the wafer ready for etching or implant doping. The aforementioned processes are generally repeated as each metal layer is fabricated, with some advanced microprocessors requiring seven or more metal layers.
As the number of layers fabricated on a wafer increase, planarity and cleanliness of the wafer surface become paramount, as minute features created on the wafer surface must line up with corresponding features on the layer below. Such features are often only a fraction of a micron wide (where a micron is one millionth of a meter) so it is critical that the wafer surface be substantially free of topological defects, as with every subsequent layer, any topological defect becomes magnified. Surface non-planarity or particulate matter on the wafer surface can lead to feature registration issues, when the components on adjacent layers do not “line up” properly, potentially leading to nonfunctional or faulty integrated circuits.
A primary challenge in wafer fabrication is the continuing reduction of defect levels. Defects potentially present on wafer surfaces include CMP slurry residue, oxides, organic contaminants, mobile ions and metallic impurities. Generally, a “killer defect” (particle) can be as small as half the size of the device linewidth. For instance, a device using 0.18-micron (&mgr;m) linewidth geometry will require that the wafer be substantially free of particles as small as 0.09 &mgr;m, and at 0.13 &mgr;m geometry, particles as small as 0.065 &mgr;m. Due to their smaller size, it is physically more difficult to remove smaller particles than larger particles, so it is beneficial to prevent deposition of particles onto the wafers as much as possible.
Increasingly complex integrated circuits utilize an increasing number of circuit elements, which in turn requires both more electrical conduction paths between circuit elements and a greater number of conductor-insulator layers to achieve these paths. This has proved problematic for several reasons. First, longer interconnect paths means increasing resistance and capacitance, which not only decreases circuit speed by increasing RC-delay times but also increases resistive power loss. Second, an increasing number of layers makes successive layer-

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