Abrading – Machine – Rotary tool
Reexamination Certificate
2001-12-21
2004-06-22
Rose, Robert A. (Department: 3723)
Abrading
Machine
Rotary tool
C451S388000
Reexamination Certificate
active
06752703
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to chemical mechanical polishing (CMP) systems, and to techniques for improving the performance and effectiveness of CMP operations. More specifically, the present invention relates to apparatus and methods for consistently releasably securing a wafer to and releasing the wafer from a CMP carrier, while reducing interference by such apparatus and methods with CMP operations performed on the wafer.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including polishing, buffing and wafer cleaning; and to perform wafer handling operations in conjunction with such CMP operations. For example, a typical semiconductor wafer may be made from silicon and, for example, may be a disk that is 200 mm or 300 mm in diameter. The 200 mm wafer may have a thickness of 0.028 inches, for example. For ease of description, the term “wafer” is used below to describe and include such semiconductor wafers and other planar structures, or substrates, that are used to support electrical or electronic circuits.
Typically, integrated circuit devices are in the form of multi-level structures fabricated on such wafers. At the wafer level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. Patterned conductive layers are insulated from other conductive layers by dielectric materials. As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material increases. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization.
In a typical CMP system, a wafer is mounted on a carrier with a surface of the wafer exposed for CMP processing. The carrier and the wafer rotate in a direction of rotation. The CMP process may be achieved, for example, when the exposed surface of the rotating wafer and an exposed surface of a polishing pad are urged toward each other by a force, and when such exposed surfaces move in respective polishing directions. For wafer handling after completion of one step of the CMP processing, a vacuum may be applied to the carrier to retain the wafer on the carrier as the carrier and the wafer are moved to a next CMP processing station. Upon completion of the CMP processing using that carrier, pressure may be applied to the carrier in a “blow off” operation to force the wafer from the carrier.
A situation has been encountered in providing apparatus and methods for retaining the wafer on the carrier during such carrier/wafer movement, and in providing the blow off pressure to the carrier to force the wafer from the carrier. This situation is described with reference to
FIG. 1A
, which shows a plan view looking upwardly to a typical prior carrier
20
. The carrier
20
is a disk-like structure having a diameter in excess of seven inches and a flat surface
21
that provides support for a protective carrier film
22
which supports a wafer
23
during the CMP processing. In
FIG. 1A
, the wafer
23
is shown cut away to expose the film
22
, and the film
22
is shown cut away to expose the carrier
20
. An exemplary six to twenty holes are typically formed through the carrier
20
. In
FIG. 1A
, six holes
24
are illustrated, each about 0.040 inches in diameter and typically formed through the prior carrier
20
at locations L
1
through L
6
across the flat surface
21
as shown in cross section in FIG.
1
B. As described below, locations L
1
through L
6
are widely spaced.
In one embodiment of the prior carrier
20
, each of the holes
24
is centered on a circular line
26
having a diameter of between six and seven inches. The circular line
26
is coaxial with a center
27
of the prior carrier
20
. Around the circular line
26
, uniform spacing of each one of the six holes
24
from all other of the holes may be about three and one-half inches, which is defined as “widely spaced” and across the diameter of the circular line
26
the hole-to-hole spacing may exceed six inches, which is within the definition of “widely spaced”. In such embodiment, the flat surface
21
of the prior carrier
20
is typically protected using a consumable layer in the form of the carrier film
22
having a thickness of about 0.020 inches and a diameter corresponding to the diameter of the prior carrier
20
. The carrier film
22
overlies the flat surface
21
. The carrier film
22
is provided with six punched holes
28
each having a diameter of about 0.060 inches. The carrier film holes
28
are centered on a similar circle having a diameter of between six and seven inches. Each carrier film hole
28
is coaxial (i.e., aligned) with the center of a corresponding one the six carrier film holes
24
.
With such background in mind, the situation that has been encountered relates to the following. Although the exemplary six carrier holes
24
and the exemplary six aligned carrier film holes
28
generally provide enough vacuum to the wafer
23
for retaining the wafer
23
on the prior carrier
20
during such carrier/wafer movement, and for applying the blow off pressure to the wafer
23
on the prior carrier
20
, when such prior carrier
20
and carrier film
22
are used with the wafer
23
in CMP operations, undesired deformation of the wafer
23
occurs. For example,
FIGS. 1C and D
depict results of examining a surface
29
of the wafer
23
that was exposed to a CMP polishing pad
36
(
FIG. 1B
) during a CMP operation using the prior carrier
20
and carrier film
22
described above.
FIG. 1C
graphically shows percent removal rate plotted against the locations L
1
through L
6
at which the carrier holes
24
and the carrier film holes
28
are spaced around the circle
26
. The removal rate is the rate at which CMP occurs on the exposed surface
29
, and may be measured in Angstrom units, for example. Although a 100% polishing removal rate is desired on the entire area of the exposed wafer surface
29
,
FIG. 1C
shows that there is a decrease (or reduction) of up to 15% in the percent removal rate.
FIG. 1D
shows that such decrease corresponds to low removal rate portions
31
of the exposed area
29
(centered at the aligned holes
24
and
28
at locations L
1
through L
6
on the wafer
23
). The portions
31
of the exposed surface
29
of the wafer
23
corresponding to the decreased polishing removal rate may also be referred to as “low polish-rate areas”and are depicted in
FIG. 1D
by many circular lines
32
centered at the centers of the respective coaxial holes
24
and
28
. The outer circular lines
33
are shown having diameter exceeding that of both of the respective holes
24
and
28
to illustrate that the low polish rate areas extend radially from such centers to distances greater than the diameter of the largest (i.e., the carrier film) hole
28
. Thus, there is an effect, termed a “field effect”, of reduced percent removal rate having a diameter significantly exceeding the diameter of the larger (carrier film) holes
28
. The low polish-rate areas, or portions,
31
of the exposed surface
29
of the wafer
23
may have a diameter of up to about one inch, for example. These low polish-rate areas may be unusable for fabricating silicon devices, add to manufacturing costs due to a need to locate such portions, and reduce the yield of the polished wafers.
This situation relating to the low polish rate areas
31
is complicated by the ongoing need to provide a way for vacuum and pressure to be applied from the prior carrier
20
through the carrier film
22
to the wafer
23
for the above-noted necessary wafer handling operations. Since th
Boyd John M.
Saldana Miguel A.
Williams Damon Vincent
Lam Research Corporation
Martine & Penilla LLP
Rose Robert A.
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