Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2003-06-24
2004-10-26
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S217000, C438S511000, C438S518000
Reexamination Certificate
active
06808970
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and, more particularly, to the implanting of ions of dopant materials into workpieces and/or substrates suitable for the fabrication of integrated circuits. More specifically, the present invention relates to a method of forming a strained surface layer into substrates during the fabrication of field effect transistors.
2. Description of the Related Art
In the last several years, the number of circuit elements manufactured on semiconductor substrates has continuously grown, and accordingly the size of circuit elements commonly fabricated has continuously decreased. Moreover, modern manufacturing technologies have developed so as to include several ion implanting steps. For instance, ion implanting steps are currently performed for the purpose of forming well structures, halo structures, source and drain regions, and the like. However, as the miniaturization of the circuit elements has developed, the need has arisen to restrict the doping profiles of the various implants within well-defined locations. That is, implantations need to be confined within regions of the substrate having dimensions in conformity with the reduced feature sizes of the circuit elements, e.g., transistors, to be formed. To obtain the shallow doping profiles required, all physical mechanisms allowing dopants to penetrate deeper into the substrate must be strictly controlled or eliminated. One important factor to be controlled is ion channeling. To accomplish this end, shallow profile doping processes often use a so-called “pre-amorphization” implantation step prior to the actual dopant implantations. In particular, an amorphous zone is usually formed during a first pre-amorphization implantation, and, during subsequent implantation processes, the doped regions (halo and source/drain regions) are formed. Commonly, heavy inert ions like germanium or xenon are implanted at an implant energy of approximately 80-200 keV.
In the following, a brief description will be given with reference to
FIGS. 1
a
-
1
c
of a typical prior art process for forming the active regions of a field effect transistor, including a typical “pre-amorphization” implanting step.
FIG. 1
a
schematically shows a MOS transistor
100
to be formed on a substrate
1
, such as a silicon wafer. Isolation structures
2
define an active region of the transistor
100
. Moreover, reference
3
relates to a polysilicon gate electrode of the MOS transistor
100
. Finally, reference
6
denotes a gate insulation layer.
In
FIGS. 1
b
-
1
c
, those parts already described with reference to
FIG. 1
a
are identified by the same reference numerals. In addition, in
FIG. 1
b
, reference
7
a
relates to an ion beam to which the substrate
1
is exposed during a “pre-amorphization” implanting process, and reference
5
a
relates to amorphous regions formed into the substrate
1
.
FIG. 1
c
shows the MOS transistor
100
once the active regions have been completed. In particular, in
FIG. 1
c
, reference
5
h
relates to halo regions formed into the substrate and references
5
S and
5
D identify the source and drain regions of the transistor
100
, respectively. Moreover, in
FIG. 1
c
, reference
4
relates to dielectric sidewall spacers formed on the sidewalls of the polysilicon line
3
.
A typical process flow for forming the active regions of the transistor
100
comprising the amorphous regions
5
a
, the halo structures
5
h
and the source and drain regions
5
S and
5
D may be summarized as follows.
Following the formation of the gate insulation layer
6
and the overlying polysilicon line
3
according to well known lithography and etching techniques (see
FIG. 1
a
), the amorphous regions
5
a
are formed during a first implant-step (see
FIG. 1
b
). To this end, the substrate
1
is exposed to an ion beam
7
a
and heavy-ions such as, for example, phosphorous, arsenic, and argon are implanted into the substrate at an implanting energy of about 80 keV.
Once the amorphous regions
5
a
have been formed as described above, the manufacturing process is resumed, and several further implanting steps are carried out for the purpose of forming the halo structures
5
h
and the source and drain regions
5
S and
5
D. In particular, during a so-called halo implanting step, boron ions in NMOS transistors and phosphorous ions in PMOS transistors are implanted at 90 keV with a dose of 2×10
13
cm
−2
. After forming the halo structures
5
h
, a subsequent implanting step is carried out for forming the source and drain extension regions (not shown) of the transistor
100
. To this end, a dose of approximately 3×10
13
-3×10
14
cm
−2
dopant ions is implanted at low energy (30-50 keV). Similar to the halo implantation step, this implantation step causes the edges of the implanted regions to be substantially aligned with the edge of the gate insulation layer
6
. Subsequently, dielectric sidewall spacers
4
are formed on the sidewalls of the polysilicon line
3
according to well known techniques, and a further heavy implantation step is carried out for implanting dopants into those regions of the substrate not covered by the polysilicon line
3
and the sidewall spacers
4
. At the end of the heavy implantation step, the source and drain regions
5
S and
5
D are formed to exhibit the desired concentration.
The prior art manufacturing process as depicted above is affected by several drawbacks. For instance, the mobility in the channel region, i.e., in the portion of the substrate underlying the gate insulation layer
6
and between the source and drain regions
5
S and
5
D, is too low when compared to the high speed and high performance required in modern transistors. Moreover, damage results in the substrate in proximity to the source-drain junction during the pre-amorphization implanting step as depicted in
FIG. 1
b
so that leakage currents may arise, leading to malfunctioning of the transistor.
Many efforts have been made and several solutions have been proposed in the art to overcome at least some of these drawbacks. In particular, it has been proposed to improve the mobility of the electrical charges in the channel region by forming a strained surface layer on the; substrate at the beginning of the manufacturing process, i.e., before forming the polysilicon structure
3
and before the usual implanting steps are carried out. In the following, a description will be given with reference to
FIGS. 2
a
-
2
d
of a typical prior art process for forming the active regions of a field effect transistor, including a typical step for generating a strained surface layer on the substrate.
FIG. 2
a
schematically shows a substrate
1
, such as a silicon wafer, on which a MOS transistor is to be formed. Isolation structures
2
define an active region of the transistor
100
. Moreover, reference
1
e
identifies a strained layer that is formed on the surface of the substrate
1
, as will be described in the following. In the particular example depicted in
FIG. 2
a
, it is assumed that the strained layer
1
e
is formed after formation of the isolation structures
2
. However, processes are known in the art according to which the strained layer
1
e
is formed first and the isolation structures
2
are formed thereafter.
In
FIGS. 2
b
-
2
c
, those parts already described with reference to
FIGS. 2
a
and
1
a
-
1
c
are identified by the same reference numerals. Accordingly, reference
7
a
in
FIG. 2
b
identifies an ion beam to which the substrate
1
is exposed for the purpose of forming amorphous regions
5
a
. Moreover, in
FIG. 2
b
, reference
6
relates to a gate insulation layer and reference
3
relates to a polysilicon line formed thereon. Finally, in
FIG. 2
c
, reference
4
relates to sidewall spacers formed on the sidewalls of the polysilicon line
3
, while the references
5
h
,
5
S and
5
D identify halo structures and source and drain regions of the transistor
100
, respectively. The poly
Feudel Thomas
Herrmann Lutz
Krueger Christian
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