Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-06
2004-02-24
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S303000, C257S295000, C257S533000
Reexamination Certificate
active
06696719
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, for example, a semiconductor memory device, having a resistance element in the peripheral circuit region and to the process for its fabrication. More particularly, the invention relates to a dynamic random access memory (DRAM) comprising a resistance element in the attached peripheral circuit region therein and an MIM or MIS structure as a cell capacitor therefor and to the process for its fabrication.
2. Description of the Prior Art
Some kinds of semiconductor devices, such as semiconductor memory devices, are composed of a memory circuit part, for example a memory cell part of a DRAM (a dynamic random access memory), which is a main constituent element thereof, and additionally attached peripheral circuit parts. A self-refresh circuit built in the DRAM is an example of the attached peripheral circuits. In the self-refresh circuit, a timer for the circuit of course includes a resistance element. Development and application of a combined installation type semiconductor memory device and a hybrid type semiconductor memory device comprising a logic circuit as an attached circuit in addition to the memory circuit are just in progress. Under such circumstances, it has been required to fabricate elements constituting various kinds of peripheral circuit parts to be formed together with a memory circuit part, which is a main constituent element, on a single substrate in the same process. For example, a resistance element is one of the elements composing those peripheral circuit parts and formed to have a desired resistance value using a conductive material with a relatively high resistivity.
On the other hand, the integration degree of the above-mentioned memory cell part is rised, and accordingly the surface area of a unit cell is considerably reduced. To accomplish the required reduction in the surface area of the unit cell, a dielectric material having a higher dielectric constant tends to be used for a cell capacitor instead of a conventionally used silicon oxide film or silicon nitride film for, for example, a layered structure of oxide
itride/oxide films. A capacitor with a MIM or MIS structure is employed using, for example, Ta
2
O
5
film or various kinds of oxides with perovskite structure as a capacitor insulation film. A high-dielectric oxide material with the above-mentioned perovskite structure to be used for the capacitor insulation film includes, for example, BST ((Ba
x
Sr
1-x
)TiO
3
) type materials.
When a silicon oxide film or a silicon nitride film is used as the capacitor insulation film in the configuration of a capacitor with the MIM or MIS structure, a polysilicon layer is commonly used for an upper electrode layer (the M layer). The polysilicon layer to be employed for the upper electrode layer may not be a low resistance layer, and indeed such having a resistivity of about 10
−3
&OHgr;cm is also employed. Further owing to the requirement in terms of functions, the polysilicon layer for the above-mentioned upper electrode layer is evenly deposited on an interlayer insulating film by a vapor phase deposition, so that the layer is used, for example, as a resistance layer of a resistance element to be composed in a peripheral circuit part. In other words, the polysilicon layer deposited on an interlayer insulating film of the peripheral circuit part is patterned in a desired shape to obtain a resistance element with a predetermined resistance value.
In the case an oxide such as BST with the perovskite structure is employed as the capacitor insulation film in the configuration of a capacitor with the MIM or MIS structure an undesired phenomenon such as mutual diffusion of formation of a low dielectric layer on the interface is caused by using polysilicon for an electrode layer. In order to avoid such an undesired phenomenon, configuration is employed where a double layer of, for example, Ti (titanium)/TiN (titanium nitride) is formed as a barrier layer to prevent mutual diffusion, or where Ru (ruthenium), Ir (iridium), or the like or its conductive oxide, e.g. RuO
2
(ruthenium oxide), IrO
02
(iridium oxide), or the like is used for an electrode layer itself. Platinum-group metals such as Ru and their oxides, which all have excellent conductivity, are suitable for an electrode material with sufficiently low resistivity to increase the integration degree and to decrease the capacitor surface area. Further, a double layer of Ti/TiN to be used for the barrier layer to prevent diffusion is also applicable to an electrode material with sufficiently low resistivity, and, even when such a barrier layer is inserted, increase of the resistance in the direction of the electrode layers (increase of series resistance) is not caused.
On the other hand, in the case the above-mentioned material such as Ru or RuO
2
, or the barrier layer such as Ti/TiN double layer is employed, the sheet resistance in the in-plane direction (the lateral direction) of the whole electrode layer is remarkably low as compared with that of a conventional polysilicon owing to the considerably low resistivity. For that, in a semiconductor device using a polysilicon layer for a conventional cell capacitor upper electrode, the same polysilicon layer is also used as the resistance layer in a resistance element for composing the peripheral circuit part, however in the case material such as Ru or RuO
2
is used for the cell capacitor upper electrode, an element configuration in which the conductive material layer for the upper electrode is used as a resistance layer of a resistance element can no longer be applicable. That is, assuming, as illustrated in
FIG. 2
, the above-mentioned Ru or RuO
2
is used for the resistance layer, there is need to employ means of significantly narrowing the line width of the resistance layer or significantly elongating the whole length of the route of the resistance pattern for increasing the resistance value of the resistance element, however it is difficult to employ such means owing to practical restriction relevant to such as the patterning precision and the element size.
SUMMARY OF THE INVENTION
Object of the Invention
Because of the above described reason, in the case material such as Ru or RuO
2
is used for the cell capacitor upper electrode, a polysilicon layer having a desired conductivity (resistivity) is required to be separately formed only for the purpose of forming the resistance element and patterned to obtain a predetermined resistance value. It is strongly required to make the element arrangement in the whole semiconductor device practically same as that in a conventional case where a polysilicon layer is used for the cell capacitor upper electrode. In company with that, if a process of composing a resistance element is carried out after a process of patterning Ru or RuO
2
of the cell capacitor upper electrode, not only the process takes additional steps but also the polysilicon layer for the resistance element has to be aligned with the patterned upper electrode and patterned at high precision. Increase of the above-mentioned extra patterning steps, especially, a photolithographic step is desirably suppressed, if possible, in the case of highly dense integration and thus an innovative proposal of a semiconductor device structure enabling fabricating a resistance element using a polysilicon layer having a desired conductivity (resistivity) while avoiding the increase of the photolithographic step.
The present invention is to solve the above-mentioned problems and the purposes of the present invention is to provide a semiconductor device structure employing an innovative structure for a plate electrode to be used in a semiconductor device, for example, a semiconductor memory device. For example, in the case of a semiconductor memory device comprising the above-mentioned resistance element composed using a cell capacitor with an MIM or MIS structure wherein a conductive material such as Ru with low resistivity is used for the upper electrod
Jackson Jerome
NEC Corporation
Nguyen Joseph
LandOfFree
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