Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-01-15
2004-12-14
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S622000, C438S618000, C257S773000
Reexamination Certificate
active
06831006
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a structure and method for eliminating metal contacts to P-well or N-well shorts when using metal studs, and more particularly eliminates metal contacts to P-well shorts when using metal contact studs by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the polysilicon forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The present invention also relates to the complementary structure and method of eliminating bitline diffusion to N-well shorts when using metal contact studs.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a structure and method for eliminating metal contacts to P-well or N-well shorts when using metal studs.
The present invention prevents a short from a metal stud to a P-well which can occur when a contact mask is misaligned with an active area (AA) mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the bitline junction depletion region or even a P-well on the active area mask sidewall to the metal stud. The present invention prevents this problem by using N+ doped polysilicon studs, wherein an outdiffusion of N+ dopant from the stud forms an N+ halo extension in the silicon, providing a reverse biased junction between the stud and the P-well. The present invention also relates to the complementary structure and method of eliminating metal contacts to N-well shorts when using metal studs.
In accordance with the teachings herein, the present invention provides the following advantages over the currently practiced, prior art technology:
it eliminates metal contacts to P-well or N-well shorts when using metal contact studs in a semiconductor device such as an embedded-DRAM or regular DRAM;
it provides contacts in a support which are self aligned to M
0
metallurgy. This enables smaller support contacts and denser layouts;
it requires no additional masks or masking steps.
The present invention also provides a structure and method for eliminating metal contacts to N-well shorts when using metal studs. The present invention prevents a short from a metal stud to an N-well which can occur when a CB (contact bitline) contact mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the bitline junction depletion region or even an N-well on the active area mask sidewall to the metal stud. The present invention prevents this problem by using P+ doped polysilicon studs, wherein an outdiffusion of P+ dopant from the stud forms a P+ halo extension in the silicon, providing a reverse biased junction between the stud and the N-well.
REFERENCES:
patent: 5293053 (1994-03-01), Malhi et al.
patent: 6339241 (2002-01-01), Mandelman et al.
patent: 6399447 (2002-06-01), Clevenger et al.
patent: 6753241 (2004-06-01), Dennison
patent: 2002/0093112 (2002-07-01), Nesbit et al.
Divakaruni Ramachandra
Mandelman Jack
Yang Haining
Abate Esq. Joseph P.
Scully Scott Murphy & Presser
Smith Brad
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