Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2003-08-04
2004-12-07
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S202000, C365S203000
Reexamination Certificate
active
06829182
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to semiconductor memories and, more specifically, to devices and methods for margin testing a semiconductor memory by, for example, equilibrating all complementary and true digit lines of the memory to ground simultaneously during a test mode.
2. State of the Art
As shown in
FIG. 1
, one conventional method for margin testing a sub-array
10
of a semiconductor memory begins with storing a supply voltage V
CC
on all memory cell capacitors
12
of the sub-array
10
. This is accomplished by writing logical “1” bits to memory cells attached to true digit lines D
0
, D
1
, etc. using sense amplifiers
14
and even row lines R
0
, R
2
, etc., and by writing logical “0” bits to memory cells attached to complementary digit lines D
0
*, D
1
*, etc. using the sense amplifiers
14
and odd row lines R
1
, R
3
, etc. A cell plate voltage DVC2 equal to one-half the supply voltage V
CC
is applied to the cell plate of each memory cell capacitor
12
.
Once each memory cell capacitor
12
has stored the supply voltage V
CC
, the row line R
0
, for example, is fired, causing the memory cells attached to the row line R
0
to dump their stored charge from their memory cell capacitors
12
onto the true digit lines D
0
, D
1
, etc. This causes the sense amplifiers
14
to pull each of the true digit lines D
0
, D
1
, etc. up to the supply voltage V
CC
, and to pull each of the complementary digit lines D
0
*, D
1
*, etc. down to ground. As a result, a full V
CC
-to-ground voltage drop is imposed across NMOS access devices
16
of the memory cells attached to the complementary digit lines D
0
*, D
1
*, etc. The V
CC
-to-ground voltage drop is maintained across the NMOS access devices
16
for a predetermined refresh interval of typically about 150 to 200 milliseconds (ms). This stresses any “leaky” NMOS access devices
16
and causes any such NMOS access devices
16
to lose significant charge from their memory cell capacitors
12
to the complementary digit lines D
0
*, D
1
*, etc. to which they are attached.
Once the predetermined refresh interval is over, all of the memory cells attached to the complementary digit lines D
0
*, D
1
*, etc. are read. Any of these cells that read out a logical “1” bit as a result of leaking excessive charge, instead of reading out the logical “0” bit they originally stored, are flagged as failing the margin test.
Once the memory cells attached to the complementary digit lines D
0
*, D
1
*, etc. have been tested, the memory cells attached to the true digit lines D
0
, D
1
, etc. are tested by firing the row line R
1
, for example. This causes the memory cells attached to the row line R
1
to dump their stored charge from their memory cell capacitors
12
onto the complementary digit lines D
0
*, D
1
*, etc. In turn, this causes the sense amplifiers
14
to pull each of the complementary digit lines D
0
*, D
1
*, etc. up to the supply voltage V
CC
, and to pull each of the true digit lines D
0
, D
1
, etc. down to ground. As a result, a full V
CC
-to-ground voltage drop is imposed across NMOS access devices
18
of the memory cells attached to the true digit lines D
0
, D
1
, etc. The V
CC
-to-ground voltage drop is maintained across the NMOS access devices
18
for another predetermined refresh interval of about 150 to 200 ins. This stresses any “leaky” NMOS access devices
18
and causes any such NMOS access devices
18
to lose significant charge from their memory cell capacitors
12
to the true digit lines D
0
, D
1
, etc. to which they are attached.
Once the predetermined refresh interval is over, all of the memory cells attached to the true digit lines D
0
, D
1
, etc. are read. Any of these cells that read out a logical “0” bit as a result of leaking excessive charge, instead of reading out the logical “1” bit they originally stored, are flagged as failing the margin test.
This conventional margin testing method thus typically takes two predetermined refresh intervals of about 150 to 200 ms. each to complete. Since row lines in different sub-arrays in a semiconductor memory typically cannot be fired simultaneously because the addressing of the row lines is local to their respective sub-arrays, this conventional method cannot be used on more than one sub-array at a time. As a result, in a semiconductor memory containing four sub-arrays, for example, the conventional method described above takes approximately 1.2 to 1.6 seconds to complete. Because of the large number of semiconductor memories that typically require margin testing during production, it would be desirable to find a margin testing method that can be completed more quickly than the method described above.
As shown in
FIG. 2
, another conventional method for margin testing a semiconductor memory has been devised to conduct margin tests more quickly than the method described above. In this method, a sense amplifier
20
includes equilibrating NMOS transistors
22
which equilibrate true and complementary digit line pairs D
0
, D
0
*, etc. to a bias voltage V
BIAS
on an equilibrate bias node
23
in response to an equilibrate signal EQ. It should be understood that an “equilibrate bias node” is a node to which a cell plate is coupled, and from which a bias voltage is globally distributed for use by equilibrating transistors throughout a semiconductor memory.
When the semiconductor memory is not in a margin test mode, a test mode signal TESTMODE is inactive, so that a PMOS transistor
24
is on and the bias voltage V
BIAS
on the equilibrate bias node
23
is equal to the cell plate voltage DVC2 on the cell plate
25
. When the semiconductor memory is in a margin test mode, the test mode signal TESTMODE is active so that the PMOS transistor
24
isolates the equilibrate bias node
23
from the cell plate
25
, and so an NMOS transistor
26
connects the equilibrate bias node
23
to a probe pad
28
positioned on the exterior of the semiconductor memory. A stressing voltage, such as ground, can then be applied to the probe pad
28
during margin testing to simultaneously stress memory cells attached to both the true and complementary digit lines D
0
, D
0
*, etc.
Because the method described immediately above does not require the firing of any row lines in order to stress memory cells, all cells in a semiconductor memory can be stressed at once using this method. As a result, this method only requires one predetermined refresh period to complete testing, no matter how many sub-arrays a semiconductor memory contains. Thus, the method dramatically improves the speed with which margin testing can be completed.
Unfortunately, the method described above with respect to
FIG. 2
has proven difficult to implement because the PMOS transistor
24
generally does not reliably isolate the equilibrate bias node
23
from the cell plate
25
. In addition, the probe pad
28
has proven to be a cumbersome addition to the exterior of a semiconductor memory.
Therefore, there is a need in the art for a device and method for margin testing a semiconductor memory that avoid the problems associated with the probe pad method described above while still providing a rapid margin testing device and method.
BRIEF SUMMARY OF THE INVENTION
Circuitry, in accordance with the invention for margin testing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes switching circuits formed within the memory. Each switching circuit can be conveniently incorporated into a sense amplifier of the memory, and each is associated with a pair of digit lines of the memory to which it selectively applies a stressing voltage at substantially the same time during a margin test mode of the memory. The stressing voltage can be ground when all the memory cells of the memory store a supply voltage level during the margin test, or it can be at the supply voltage level when all the memory cells store a ground voltage level during the margin test. The switching circuits can apply the stressing voltage to the digit line pairs through equi
Mai Son
Micro)n Technology, Inc.
TraskBritt
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